NXP Semiconductors
PH9025L
N-channel TrenchMOS logic level FET
3
VGS(th)
(V)
2
1.5
1
0.5
max
typ
min
003aab272
10−1
ID
(A)
10−2
10−3
10−4
10−5
003aab938
min typ max
0
-60
0
60
120
180
Tj (°C)
ID = 1 mA; VDS = VGS
Fig 9. Gate-source threshold voltage as a function of
junction temperature
10−6
0
1
2
3
VGS (V)
Tj = 25 °C; VDS = 5 V
Fig 10. Sub-threshold drain current as a function of
gate-source voltage
10
VGS
(V)
8
VDS = 12 V
ID = 10 A
Tj = 25 °C
003aab551
6
4
2
0
0
7.5
15
22.5
30
QG (nC)
ID = 10 A; VDS = 12 V
Fig 11. Gate-source voltage as a function of gate
charge; typical values
VDS
ID
VGS(pl)
VGS(th)
VGS
QGS1 QGS2
QGS
QGD
QG(tot)
003aaa508
Fig 12. Gate charge waveform definitions
PH9025L_1
Product data sheet
Rev. 01 — 23 August 2007
© NXP B.V. 2007. All rights reserved.
7 of 12