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ML145027EP Просмотр технического описания (PDF) - Unspecified

Номер в каталогеML145027EP ETC
Компоненты ОписаниеEncoder and Decoder Pairs CMOS
ML145027EP Datasheet PDF : 19 Pages
First Prev 11 12 13 14 15 16 17 18 19
ML145026, ML145027, ML145028
LANSDALE Semiconductor, Inc.
ML145027 AND ML145028 TIMING
To verify the ML145027 or ML145028 timing, check the-
waveforms on C1 (Pin 7) and R2/C2 (Pin 10) as compared to
the incoming data waveform on Din (Pin 9).
The R–C decay seen on C1 discharges down to 1/3 VDD
before being reset to VDD. This point of reset (labelled “DOS”
in Figure 15) is the point in time where the decision is made
whether the data seen on Din is a 1 or 0. DOS should not be
too close to the Din data edges or intermittent operation may
The other timing to be checked on the ML145027 and
ML145028 is on R2/C2 (see Figure 16). The R–C decay is
continually reset to VDD as data is being transmitted. Only
between words and after the end–of–transmission (EOT) does
R2/C2 decay significantly from VDD. R2/C2 can be used to
identify the internal end–of–word (EOW) timing edge which is
generated when R2/C2 decays to 2/3 VDD. The internal EOT
timing edge occurs when R2/C2 decays to 1/3 VDD. When the
waveform is being observed, the R–C decay should go down
between the 2/3 and 1/3 VDD levels, but not too close to either
level before data transmission on Din resumes.
Verification of the timing described above should ensure a
good match between the ML145026 transmitter and the
ML145027 and ML145028 receivers.
C1 2/3
Figure 15. R ÐC Decay on Pin 7 (C1)
R2/C2 1/3
F igure 16. R ÐC Decay on P in 10 (R 2/C 2)
Page 13 of 19
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