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ML12040-4P Просмотр технического описания (PDF) - LANSDALE Semiconductor Inc.

Номер в каталогеML12040-4P LANSDALE
LANSDALE Semiconductor Inc. LANSDALE
Компоненты ОписаниеPhase–Frequency Detector
ML12040-4P Datasheet PDF : 5 Pages
1 2 3 4 5
LANSDALE Semiconductor, Inc.
Legacy Applications Information
The ML12040 is a logic network designed for use as a phase
comparator for MECL–compatible input signals. It determines
the “lead” or “lag” phase relationship and the time difference
between the leading edges of the waveforms. Since these edges
occur only once per cycle, the detector has a range of ±2π radians.
Operation of the device may be illustrated by assuming two
waveforms, R and V (Figure 2), of the same frequency but dif-
fering in phase. If the logic had established by past history that
R was leading V, the U output of the detector (pin 4) would
produce a positive pulse width equal to the phase difference
and the D output (Pin 11 ) would simply remain low.
On the other hand, it is also possible that V was leading R
(Figure 2), giving rise to a positive pulse on the D output and a
constant low level on the U output pin. Both outputs for the
sample condition are valid since the determination of lead or
lag is dependent on past edge crossing and initial conditions at
start–up. A stable phase–locked loop will result from either
Phase error information is contained in the output duty cycle
that is, the ratio of the output pulse width to total period. By inte-
grating or low–pass filtering the outputs of the detector and shift-
ing the level to accommodate ECL swings, usable analog infor-
mation for the voltage controlled oscillator can be developed. A
circuit useful for this function is shown in Figure 3.
Proper level shifting is accomplished by differentially driving
the operational amplifier from the normally high outputs of the
phase detector (U and D). Using this technique the quiescent
differential voltage to the operational amplifier is zero (assum-
ing matched “1” levels from the phase detector). The U and D
outputs are then used to pass along phase information to the
operational amplifier. Phase error summing is accomplished
through resistors R1 connected to the inputs of the operational
amplifier. Some R–C filtering imbedded within the input net-
work (Figure 3) may be very beneficial since the very narrow
correctional pulses of the ML12040 would not normally be
integrated by the amplifier. Phase detector gain for this config-
uration is approximately 0.16 volts/radian.
System phase error stems from input offset voltage in the
operational amplifier, mismatching of nominally equal resis-
tors, and mismatching of phase detector “high” states between
the outputs used for threshold setting and phase measuring. All
these effects are reflected in the gain constant. For example, a
16 mV offset voltage in the amplifier would cause an error of
0.016/0.16 = 0.1 radian or 5.7 degrees of error. Phase error can
be trimmed to zero initially by trimming either input offset or
one of the threshold resistors (R1 in Figure 3). Phase error
over temperature depends on how much the offending parame-
ters drift.
Figure 2. Timing Diagram
R Leads V
(D Output = “0”)
V Leads R
(D Output = “0”)
Figure 3. Typical Filter and Summing Network
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The ML12040 is a phase–frequency detector intended for use in systems requiring zero phase and frequency difference at lock. In combination with a voltage controlled oscillator (such as the ML12149), it is useful in a broad range of phase–locked loop applications.

• Operating Frequency = 80 MHz Typical
• Operating Temperature Range TA= 0° to 75°C

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