M13S64164A-6TIG View Datasheet(PDF) - [Elite Semiconductor Memory Technology Inc.
Part Name
Description
Manufacturer
M13S64164A-6TIG
[Elite Semiconductor Memory Technology Inc.
M13S64164A-6TIG Datasheet PDF : 49 Pages
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ESMT
M13S64164A
Operation Temperature Condition -40°C~85°C
Command Truth Table
COMMAND
Register
Register
Refresh
Extended MRS
Mode Register Set
Auto Refresh
Self
Refresh
Entry
Exit
A11,
CKEn-1 CKEn CS RAS CAS WE DM BA0,1 A10/AP A9~A0 Note
H
XLL
L
LX
OP CODE
1,2
H
XLL
L
LX
OP CODE
1,2
H
3
H
LL
L
HX
X
L
3
LH
H
H
3
L
H
X
X
HX
X
X
3
Bank Active & Row Addr.
H
Read & Auto Precharge Disable
Column
H
Address Auto Precharge Enable
XLL
H
HX
V
XLH
L
HX
V
Row Address
L
4
Column
H
Address 4
Write & Auto Precharge Disable
Column
H
Address Auto Precharge Enable
XLH
L
LX
V
L
4
Column
H
Address 4,6
Burst Stop
H
XLH
H
LX
X
7
Precharge
Bank Selection
All Banks
V
L
H
XLL
H
LX
X
H
X
5
HX
X
X
Entry
H
L
X
Active Power Down
LV
V
V
X
Exit
L
HXX
X
XX
HX
X
X
Entry
H
L
X
Precharge Power Down
Mode
LH
H
H
X
HX
X
X
Exit
L
H
X
LV
V
V
DM
H
X
V
X
8
HX
X
X
No Operation Command
H
X
X
X
LH
H
H
(V = Valid, X = Don’t Care, H = Logic High, L = Logic Low)
1. OP Code: Operand Code. A0~A11 & BA0~BA1 : Program keys. (@EMRS/MRS)
2. EMRS/MRS can be issued only at all banks precharge state.
A new command can be issued 1 clock cycles after EMRS or MRS.
3. Auto refresh functions are same as the CBR refresh of DRAM.
The automatical precharge without row precharge command is meant by “Auto”..
Auto/self refresh can be issued only at all banks precharge state.
4. BA0~BA1 : Bank select addresses.
If both BA0 and BA1 are “Low” at read, write, row active and precharge, bank A is selected.
If BA0 is “High” and BA1 is “Low” at read, write, row active and precharge, bank B is selected.
If BA0 is “Low” and BA1 is “High” at read, write, row active and precharge, bank C is selected.
If both BA0 and BA1 are “High” at read, write, row active and precharge, bank D is selected.
5. If A10/AP is “High” at row precharge, BA0 and BA1 are ignored and all banks are selected.
6. During burst write with auto precharge, new read/write command can not be issued.
Another bank read/write command can be issued after the end of burst.
New row active of the associated bank can be issued at tRP after end of burst.
7. Burst stop command is valid at every burst length.
8. DM sampling at the rising and falling edges of the DQS and Data-in are masked at the both edges (Write DM latency is 0).
Elite Semiconductor Memory Technology Inc.
Publication Date : Mar. 2009
Revision : 1.0
8/49
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