M13S64164A View Datasheet(PDF) - [Elite Semiconductor Memory Technology Inc.

Part Name

Description

Manufacturer

M13S64164A

1M x 16 Bit x 4 Banks Double Data Rate SDRAM

[Elite Semiconductor Memory Technology Inc. 

ESMT

M13S64164A

Operation Temperature Condition -40°C~85°C

1. For the earliest possible Precharge command following a Write burst without interrupting the burst, the minimum time for write

recovery is defined by tWR.

2. When a precharge command interrupts a Write burst operation, the data mask pin, DQ, is used to mask input data during the

time between the last valid write data and the rising clock edge in which the Precharge command is given. During this time, the

DQS input is still required to strobe in the state of DM.

The minimum time for write recovery is defined by tWR.

3. For a Write with autoprecharge command, a new Bank Activate command may be issued to the same bank after tWR + tRP where

tWR + tRP starts on the falling DQS edge that strobed in the last valid data and ends on the rising clock edge that strobes in the

Bank Activate commands. During write with autoprecharge, the initiation of the internal precharge occurs at the same time as

the earliest possible external Precharge command without interrupting the Write burst as described in 1 above.

4. In all cases, a Precharge operation cannot be initiated unless tRAS(min) [minimum Bank Activate to Precharge time] has been

satisfied. This includes Write with autoprecharge commands where tRAS(min) must still be satisfied such that a Write with

autoprecharge command has the same timing as a Write command followed by the earliest possible Precharge command

which does not interrupt the burst.

Burst Stop

The burst stop command is initiated by having RAS and CAS high with CS and WE low at the rising edge of the clock

(CLK). The burst stop command has the fewest restriction making it the easiest method to use when terminating a burst read

operation before it has been completed. When the burst stop command is issued during a burst read cycle, the pair of data and

DQS (Data Strobe) go to a high impedance state after a delay which is equal to the CAS latency set in the mode register. The

burst stop command, however, is not supported during a write burst operation.

<Burst Length = 4, CAS Latency = 3 >

0

1

CL K

CL K

COMMAND READ A

B u rs t S t op

2

NOP

3

NOP

4

NOP

5

6

7

8

NOP

NOP

NOP

NOP

CA S Lat en cy= 3

DQS

DQ's

Dout 0 Dout 1

Elite Semiconductor Memory Technology Inc.

Publication Date : Mar. 2009

Revision : 1.0

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