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LT1167CS8 View Datasheet(PDF) - Linear Technology

Part NameLT1167CS8 Linear
Linear Technology Linear
DescriptionSingle Resistor Gain Programmable, Precision Instrumentation Amplifier
LT1167CS8 Datasheet PDF : 20 Pages
First Prev 11 12 13 14 15 16 17 18 19 20
LT1167
BLOCK DIAGRA
V+
–IN 2
R3
400
V
RG 1
RG 8
V+
+IN 3
R4
400
V
VB
+
A1
C1
Q1
R1
24.7k
VB
+
A2
C2
Q2
R2
24.7k
R5
R6
10k
10k
6 OUTPUT
A3
+
V
R7
R8
10k
10k
5 REF
V
7 V+
4 V
PREAMP STAGE
DIFFERENCE AMPLIFIER STAGE
1167 F01
Figure 1. Block Diagram
U
THEORY OF OPERATIO
The LT1167 is a modified version of the three op amp
instrumentation amplifier. Laser trimming and mono-
lithic construction allow tight matching and tracking of
circuit parameters over the specified temperature range.
Refer to the block diagram (Figure 1) to understand the
following circuit description. The collector currents in Q1
and Q2 are trimmed to minimize offset voltage drift, thus
assuring a high level of performance. R1 and R2 are
trimmed to an absolute value of 24.7k to assure that the
gain can be set accurately (0.05% at G = 100) with only
one external resistor RG. The value of RG determines the
transconductance of the preamp stage. As RG is reduced
for larger programmed gains, the transconductance of
the input preamp stage increases to that of the input
transistors Q1 and Q2. This increases the open-loop gain
when the programmed gain is increased, reducing the
input referred gain related errors and noise. The input
voltage noise at gains greater than 50 is determined only
by Q1 and Q2. At lower gains the noise of the difference
amplifier and preamp gain setting resistors increase the
noise. The gain bandwidth product is determined by C1,
C2 and the preamp transconductance which increases
with programmed gain. Therefore, the bandwidth does
not drop proportionally to gain.
The input transistors Q1 and Q2 offer excellent matching,
which is inherent in NPN bipolar transistors, as well as
picoampere input bias current due to superbeta process-
ing. The collector currents in Q1 and Q2 are held constant
due to the feedback through the Q1-A1-R1 loop and
Q2-A2-R2 loop which in turn impresses the differential
input voltage across the external gain set resistor RG.
Since the current that flows through RG also flows through
R1 and R2, the ratios provide a gained-up differential volt-
age,G = (R1 + R2)/RG, to the unity-gain difference amplifier
A3. The common mode voltage is removed by A3, result-
ing in a single-ended output voltage referenced to the
voltage on the REF pin. The resulting gain equation is:
VOUT – VREF = G(VIN+ – VIN–)
where:
G = (49.4k/ RG) + 1
solving for the gain set resistor gives:
RG = 49.4k/(G – 1)
11
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