SI-46001 View Datasheet(PDF) - Micrel
Part Name
Description
Manufacturer
SI-46001 Datasheet PDF : 54 Pages
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Micrel, Inc.
KSZ8041NL/RNL
Strapping Options – KSZ8041NL
Pin Number
15
14
13
Pin Name
PHYAD2
PHYAD1
PHYAD0
18
CONFIG2
29
CONFIG1
28
CONFIG0
20
ISO
31
SPEED
16
DUPLEX
Type(1)
Ipd/O
Ipd/O
Ipu/O
Ipd/O
Ipd/O
Ipd/O
Ipd/O
Ipu/O
Ipu/O
Pin Function
The PHY Address is latched at power-up / reset and is configurable to any value from
1 to 7.
The default PHY Address is 00001.
PHY Address bits [4:3] are always set to ‘00’.
The CONFIG[2:0] strap-in pins are latched at power-up / reset and are defined as
follows:
CONFIG[2:0] Mode
000
MII (default)
001
RMII
010
Reserved – not used
011
Reserved – not used
100
MII 100Mbps Preamble Restore
101
Reserved – not used
110
Reserved – not used
111
Reserved – not used
ISOLATE mode
Pull-up = Enable
Pull-down (default) = Disable
During power-up / reset, this pin value is latched into register 0h bit 10.
SPEED mode
Pull-up (default) = 100Mbps
Pull-down = 10Mbps
During power-up / reset, this pin value is latched into register 0h bit 13 as the Speed
Select, and also is latched into register 4h (Auto-Negotiation Advertisement) as the
Speed capability support.
DUPLEX mode
Pull-up (default) = Half Duplex
Pull-down = Full Duplex
During power-up / reset, this pin value is latched into register 0h bit 8 as the Duplex
Mode.
30
NWAYEN
Ipu/O
Nway Auto-Negotiation Enable
Pull-up (default) = Enable Auto-Negotiation
Pull-down = Disable Auto-Negotiation
During power-up / reset, this pin value is latched into register 0h bit 12.
Note:
1. Ipu/O = Input with internal pull-up (40K +/-30%) during power-up/reset; output pin otherwise.
Ipd/O = Input with internal pull-down (40K +/-30%) during power-up/reset; output pin otherwise.
Pin strap-ins are latched during power-up or reset. In some systems, the MAC receive input pins may drive high during
power-up or reset, and consequently cause the PHY strap-in pins on the MII/RMII signals to be latched high. In this
case, it is recommended to add 1K pull-downs on these PHY strap-in pins to ensure the PHY does not strap-in to
ISOLATE mode, or is not configured with an incorrect PHY Address.
September 2010
14
M9999-090910-1.4
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