OA87C20XX-64QT View Datasheet(PDF) - Unspecified

Part Name

Description

Manufacturer

OA87C20XX-64QT

CMOS Single-Chip 8-Bit Microcontroller with A/D Converter & VFD Driver

Unspecified 

HMS81C2012A/2020A

12.3 8-bit Compare Output (16-bit)

The HMS81C20xxA has a function of Timer Compare

Output. To pulse out, the timer match can goes to port

pin(T0O, T1O) as shown in Figure 12-2 and Figure 12-7.

Thus, pulse out is generated by the timer match. These op-

eration is implemented to pin, T0O, PWM1O/T1O.

In this mode, the bit PWM1O/T1O of R5 function register

(R5FUNC.6) should be set to "1", and the bit PWM1E of

timer1 mode register (TM1) should be set to "0". In addi-

12.4 8-bit Capture Mode

The Timer 0 capture mode is set by bit CAP0 of timer

mode register TM0 (bit CAP1 of timer mode register TM1

for Timer 1) as shown in Figure 12-8.

As mentioned above, not only Timer 0 but Timer 1 can also

be used as a capture mode.

The Timer/Counter register is increased in response inter-

nal or external input. This counting function is same with

normal timer mode, and Timer interrupt is generated when

timer register T0 (T1) increases and matches TDR0

(TDR1).

This timer interrupt in capture mode is very useful when

the pulse width of captured signal is more wider than the

maximum period of Timer.

For example, in Figure 12-10, the pulse width of captured

signal is wider than the timer data value (FFH) over 2

times. When external interrupt is occurred, the captured

value (13H) is more little than wanted value. It can be ob-

tion, 16-bit Compare output mode is available, also.

This pin output the signal having a 50 : 50 duty square

wave, and output frequency is same as below equation.

fCOMP = 2-----×-----P---r--O-e--s-s--cc--a-i--l-ll-e-a--r-t--i-Vo---na---l--Fu---er---e-×-q---u-(--Te---n-D--c---yR-----+-----1----)-

tained correct value by counting the number of timer over-

flow occurrence.

Timer/Counter still does the above, but with the added fea-

ture that a edge transition at external input INTx pin causes

the current value in the Timer x register (T0,T1), to be cap-

tured into registers CDRx (CDR0, CDR1), respectively.

After captured, Timer x register is cleared and restarts by

hardware.

Note: The CDRx, TDRx and Tx are in same address. In

the capture mode, reading operation is read the CDRx, not

Tx because path is opened to the CDRx, and TDRx is only

for writing operation.

It has three transition modes: "falling edge", "rising edge",

"both edge" which are selected by interrupt edge selection

register IEDS (Refer to External interrupt section). In ad-

dition, the transition at INTx pin generate an interrupt.

52

SEP. 2004 Ver 2.00

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