Watchdog Timer Control
Figure 11-2 shows the watchdog timer control register.
The watchdog timer is automatically disabled after reset.
The CPU malfunction is detected during setting of the de-
tection time, selecting of output, and clearing of the binary
counter. Clearing the binary counter is repeated within the
If the malfunction occurs for any cause, the watchdog tim-
er output will become active at the rising overflow from
the binary counters unless the binary counter is cleared. At
this time, when WDTON=1, a reset is generated, which
drives the RESET pin to low to reset the internal hardware.
When WDTON=0, a watchdog timer interrupt (WDTIF) is
The watchdog timer temporarily stops counting in the
STOP mode, and when the STOP mode is released, it au-
tomatically restarts (continues counting).
W WW W
INITIAL VALUE: 0111_1111B
7-bit compare data
Clear count flag
0: Free-run count
1: When the WDTCL is set to "1", binary counter
is cleared to “0”. And the WDTCL becomes “0” automatically
after one machine cycle. Counter count up again.
The WDTON bit is in register CKCTLR.
Figure 11-2 WDTR: Watchdog Timer Data Register
Example: Sets the watchdog timer detection time to 0.5 sec at 4.19MHz
detection time :
;Select 1/2048 clock source, WDTON ← 1, Clear Counter
SEP. 2004 Ver 2.00