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FSEZ1016A View Datasheet(PDF) - Fairchild Semiconductor

Part Name
Description
Manufacturer
FSEZ1016A
Fairchild
Fairchild Semiconductor Fairchild
FSEZ1016A Datasheet PDF : 16 Pages
First Prev 11 12 13 14 15 16
Physical Dimensions
6.20
5.80
5.00
4.80
3.81
8
A
5
B
4.00
3.80
1.75
0.65
5.60
PIN ONE
1
INDICATOR
(0.33)
4
1.27
0.25 M C B A
1.27
LAND PATTERN RECOMMENDATION
1.75 MAX
R0.10
R0.10
0.90
0.406
0.25
0.10
C
SEE DETAIL A
0.25
0.19
0.51
0.33
0.10 C
0.50
0.25
x
45°
GAGE PLANE
OPTION A - BEVEL EDGE
0.36
OPTION B - NO BEVEL EDGE
SEATING PLANE
(1.04)
DETAIL A
SCALE: 2:1
NOTES:
A) THIS PACKAGE CONFORMS TO JEDEC
MS-012 VARIATION AA EXCEPT FOR MISSING PIN 7.
B) ALL DIMENSIONS ARE IN MILLIMETERS.
C) DIMENSIONS DO NOT INCLUDE MOLD
FLASH OR BURRS.
D) DRAWING FILENAME: M07AREV2
Figure 33.
7-Lead, Small-Outline Integrated Circuit Package (SOIC)
Package drawings are provided as a service to customers considering Fairchild components. Drawings may change in any manner
without notice. Please note the revision and/or date on the drawing and contact a Fairchild Semiconductor representative to verify or
obtain the most recent revision. Package specifications do not expand the terms of Fairchild’s worldwide terms and conditions, specifically the
warranty therein, which covers Fairchild products.
Always visit Fairchild Semiconductor’s online packaging area for the most recent package drawings:
http://www.fairchildsemi.com/packaging/.
© 2009 Fairchild Semiconductor Corporation
FSEZ1016A • Rev. 1.0.2
15
www.fairchildsemi.com
 

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