FlashFlex51 MCU
SST89C54 / SST89C58
Preliminary Specifications
STATUS OF THE SECURITY LOCK
available for read operation via Byte-Verify. In the third
level, three different options are available: Block 1 Hard
The three bits that indicate the SST89C54/58 security lock
status are located in SFST[7:5]. As shown in Figure 19 and
Lock / Block 0 SoftLock, SoftLock on both blocks, and Hard
Lock on both blocks. Locking both blocks is the same as
1
Table 8, the three security lock bits control the lock status Level 2 except read operation isn’t available. The fourth
of the primary and secondary blocks of memory. There are
four distinct levels of security lock status. In the first level,
level of security is the most secure level operation. It
doesn’t allow read/write of internal memory or boot from
2
none of the security lock bits are programmed and both external memory. Please note that for unused combina-
blocks are unlocked. In the second level, although, both
blocks are now locked and cannot be written, they are
tions of the security lock bit the chip will default to Level 4
status.
3
UUU/NN
Level 1
4
PUU/LL
Level 2
5
6
UPU/SS
UUP/LS
Level 3
PPU/LL
=
PUP/LL
7
PPP/LL
Level 4
8
Notes:
344 ILL F38.1
1. P = Programmed (Cell logic state = 0), U = Unprogrammed (Cell logic state = 1),
9
N = Not Locked, L = Hard Locked, S = SoftLocked
FIGURE 19: SECURITY LOCK LEVELS
TABLE 8: SECURITY LOCK OPTIONS
10
Security Lock Bits
Security Status of: Security Type
Level SFST[7:5] 11 21 31 Block 1 Block 0
11
1
000
U U U Unlock Unlock No Security Features are Enabled.
2
100
P
U
U Hard Lock Hard Lock MOVC instructions executed from external
program memory are disabled from fetching
12
code bytes from internal memory, EA# is
sampled and latched on Reset, and further
programming of the flash is disabled.
13
3
110
P
P
U Hard Lock Hard Lock Level 2 plus Verify disabled, both blocks locked.
101
P
U
P
14
010
U
P
U SoftLock SoftLock Level 2 plus verify disable. code in Block 1
can program Block 0 and vice versa.
001
U
U
P Hard Lock SoftLock Level 2 plus verify disabled, code in Block 1
can program Block 0.
15
4
111
P
P
P Hard Lock Hard Lock Same as Level 3, but external boot is
Notes:
disabled.
344 PGM T8.4
16
1 1, 2, and 3, respectively, refer to the first, second, and third security lock bits.
2 P = Programmed (Cell logic state = 0), U = Unprogrammed (Cell logic state = 1).
3 SFST[7:5] = Security Lock Decoding Bits (SECD)
4 All unused combinations default to level 4, “PPP”.
© 2000 Silicon Storage Technology, Inc.
33
344-2 8/00