CS48500 Data Sheet
32-bit Audio Decoder DSP Family
5.10 Switching Characteristics — Serial Control Port - SPI Master Mode
Parameter
SCP_CLK frequency1
SCP_CS# falling to SCP_CLK rising 2
Symbol Min
fspisck
-
tspicss
-
Typical
11*DCLKP +
(SCP_CLK PERIOD)/2
Max Units
25 MHz
-
ns
SCP_CLK low time
tspickl
20
-
ns
SCP_CLK high time
tspickh
20
-
ns
Setup time SCP_MISO input
Hold time SCP_MISO input
SCP_CLK low to SCP_MOSI output valid
T SCP_CLK low to SCP_CS# falling
F SCP_CLK low to SCP_CS# rising
tspidsu
9
tspidh
5
tspidov
-
tspicsl
7
tspicsh
-
11*DCLKP +
(SCP_CLK PERIOD)/2
-
ns
-
ns
8
ns
-
ns
-
ns
Bus free time between active SCP_CS#
tspicsx
A SCP_CLK falling to SCP_MOSI output high-Z
tspidz
-
3*DCLKP
-
ns
20
ns
R 1.The specification fspisck indicates the maximum speed of the hardware. The system designer should be
aware that the actual maximum speed of the communication port may be limited by the firmware applica-
D tion.
2.SCP_CLK PERIOD refers to the period of SCP_CLK as being used in a given application. It does not refer
to a tested parameter
L I .
TIA PH tspicss
N L EE_CS#
E E tspicsl
tspickl
0
1
2
6
7
0
5
ID D SCP_CLK
fspisck
tspickh
F SCP_MISO
CON SCP_MOSI
A6
tspidsu
A5
tspidh
A0 R/W MSB
tspidov
MSB
tspicsx
6
7
tspicsh
LSB
LSB
tspidz
Figure 4. Serial Control Port - SPI Master Mode Timing
DS734A3
©Copyright 2006 Cirrus Logic, Inc.
17
CONFIDENTIAL