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BM29F040 View Datasheet(PDF) - Fujitsu

Part NameDescriptionManufacturer
BM29F040 FLASH MEMORY CMOS 4M (512K ×8) BIT Fujitsu
Fujitsu Fujitsu
BM29F040 Datasheet PDF : 40 Pages
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MBM29F040C-55/-70/-90
s AC CHARACTERISTICS
• Read Only Operations Characteristics
Parameter
Symbols
JEDEC Standard
Description
Test Setup
-55
(Note1)
-70
(Note2)
-90
(Note2)
Unit
tAVAV
tRC
Read Cycle Time
Min. 55
70
90 ns
tAVQV
tACC
Address to Output Delay
CE = VIL
OE = VIL
Max.
55
70
90 ns
tELQV
tCE
Chip Enable to Output Delay
OE = VIL Max. 55
70
90 ns
tGLQV
tOE
Output Enable to Output Delay
— Max. 30
30
35 ns
tEHQZ
tDF
Chip Enable to Output HIGH-Z
— Max. 20
20
20 ns
tGHQZ
tDF
Output Enable to Output HIGH-Z
— Max. 20
20
20 ns
tAXQX
tOH
Output Hold Time From
Addresses,
Min.
0
0
0
ns
CE or OE, Whichever Occurs First
Note: 1. Test Conditions:
Output Load: 1 TTL gate and 30 pF
Input rise and fall times: 5 ns
Input pulse levels: 0.0 V to3.0 V
Timing measurement reference level
Input: 1.5 V
Output: 1.5 V
Note: 2. Test Conditions:
Oput Load: 1 TTL gate and 100 pF
Input rise and fall times: 5 ns
Input pulse levels: 0.45 V to 2.4 V
Timing measurement reference level
Input: 0.8 and 2.0 V
Output: 0.8 and 2.0 V
Device
Under
Test
CL
5.0 V
IN3064
or Equivalent
2.7 k
6.2 k
Diodes = IN3064
or Equivalent
Note: 1.CL = 30 pF including jig capacitance
2.CL = 100 pF including jig capacitance
Figure 4 Test Conditions
22
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