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BM29F040 View Datasheet(PDF) - Fujitsu

Part NameDescriptionManufacturer
BM29F040 FLASH MEMORY CMOS 4M (512K ×8) BIT Fujitsu
Fujitsu Fujitsu
BM29F040 Datasheet PDF : 40 Pages
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Read/Reset Command
The read or reset operation is initiated by writing the Read/Reset command sequence into the command register.
Microprocessor read cycles retrieve array data from the memory. The device remains enabled for reads until the
command register contents are altered.
The device will automatically power-up in the read/reset state. In this case, a command sequence is not required
to read data. Standard microprocessor read cycles will retrieve array data. This default value ensures that no
spurious alteration of the memory content occurs during the power transition. Refer to the AC Read
Characteristics and Waveforms for the specific timing parameters.
Autoselect Command
Flash memories are intended for use in applications where the local CPU alters memory contents. As such,
manufacture and device codes must be accessible while the device resides in the target system. PROM
programmers typically access the signature codes by raising A9 to a high voltage (VID = 11.5 V to 12.5). However,
multiplexing high voltage onto the address lines is not generally desired system design practice.
The device contains an Autoselect command operation to supplement traditional PROM programming
methodology. The operation is initiated by writing the Autoselect command sequence into the command register.
Following the command write, a read cycle from address XX00H retrieves the manufacture code of 04H. A read
cycle from address XX01H returns the device code A4H. (see Table 3.) All manufacturer and device codes will
exhibit odd parity with the MSB (DQ7) defined as the parity bit.
Sector state (protection or unprotection) will be informed address XX02H.
Scanning the sector addresses (A16, A17, A18) while (A6, A1, A0) = (0, 1, 0) will produce a logical “1” at device
output DQ0 for a protected sector. The programming verification should be perform margin mode on the protected
sector. (See Table 2 and 3.)
To terminate the operation, it is necessary to write the Read/Reset command sequence into the register, and
also to write the Autoselect command during the operation, execute it after writing Read/Reset command
Byte Programming
The device is programmed on a byte-by-byte basis. Programming is a four bus cycle operation. There are two
“unlock” write cycles. These are followed by the program setup command and data write cycles. Addresses are
latched on the falling edge of CE or WE, whichever happens later and the data is latched on the rising edge of
CE or WE, whichever happens first. The rising edge of CE or WE (whichever happens first) begins programming.
Upon executing the Embedded Program Algorithm command sequence, the system is not required to provide
further controls or timings. The device will automatically provide adequate internally generated program pulses
and verify the programmed cell margin.
The automatic programming operation is completed when the data on DQ7 is equivalent to data written to this
bit (See Write Operation Status section.) at which time the device returns to the read mode and addresses are
no longer latched. (See Table 6, Hardware Sequence Flags.) Therefore, the device requires that a valid address
to the device be supplied by the system at this particular instance of time. Hence, Data Polling must be performed
at the memory location which is being programmed.
Any commands written to the chip during this period will be ignored.
Programming is allowed in any sequence and across sector boundaries. Beware that a data “0” cannot be
programmed back to a “1”. Attempting to do so may either hang up the device (Exceed timing limits.), or result
in an apparent success according to the data polling algorithm but a read from reset/read mode will show that
the data is still “0”. Only erase operations can convert “0”s to “1”s.
Figure 13 illustrates the Embedded ProgramTM Algorithm using typical command strings and bus operations.
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