AM29F040B-120EC View Datasheet(PDF) - Spansion Inc.

Part Name

Description

Manufacturer

AM29F040B-120EC

4 Megabit (512 K x 8-Bit) CMOS 5.0 Volt-only/ Uniform Sector Flash Memory

Spansion Inc. 

DATA SHEET

DQ6: Toggle Bit I

Toggle Bit I on DQ6 indicates whether an Embedded

Program or Erase algorithm is in progress or complete,

or whether the device has entered the Erase Suspend

mode. Toggle Bit I may be read at any address, and is

valid after the rising edge of the final WE# pulse in the

command sequence (prior to the program or erase op-

eration), and during the sector erase time-out.

During an Embedded Program or Erase algorithm op-

eration, successive read cycles to any address cause

DQ6 to toggle. (The system may use either OE# or

CE# to control the read cycles.) When the operation is

complete, DQ6 stops toggling.

After an erase command sequence is written, if all sec-

tors selected for erasing are protected, DQ6 toggles for

approximately 100 µs, then returns to reading array

data. If not all selected sectors are protected, the Em-

bedded Erase algorithm erases the unprotected

sectors, and ignores the selected sectors that are

protected.

The system can use DQ6 and DQ2 together to deter-

mine whether a sector is actively erasing or is erase-

suspended. When the device is actively erasing (that is,

the Embedded Erase algorithm is in progress), DQ6

toggles. When the device enters the Erase Suspend

mode, DQ6 stops toggling. However, the system must

also use DQ2 to determine which sectors are erasing

or erase-suspended. Alternatively, the system can use

DQ7 (see the subsection on “DQ7: Data# Polling”).

If a program address falls within a protected sector,

DQ6 toggles for approximately 2 µs after the program

command sequence is written, then returns to reading

array data.

DQ6 also toggles during the erase-suspend-program

mode, and stops toggling once the Embedded Pro-

gram algorithm is complete.

The Write Operation Status table shows the outputs for

Toggle Bit I on DQ6. Refer to Figure 4 for the toggle bit

algorithm, and to the Toggle Bit Timings figure in the

“AC Characteristics” section for the timing diagram.

The DQ2 vs. DQ6 figure shows the differences be-

tween DQ2 and DQ6 in graphical form. See also the

subsection on “DQ2: Toggle Bit II”.

DQ2: Toggle Bit II

The “Toggle Bit II” on DQ2, when used with DQ6, indi-

cates whether a particular sector is actively erasing

(that is, the Embedded Erase algorithm is in progress),

or whether that sector is erase-suspended. Toggle Bit

II is valid after the rising edge of the final WE# pulse in

the command sequence.

DQ2 toggles when the system reads at addresses

within those sectors that have been selected for era-

sure. (The system may use either OE# or CE# to

control the read cycles.) But DQ2 cannot distinguish

whether the sector is actively erasing or is erase-sus-

pended. DQ6, by comparison, indicates whether the

device is actively erasing, or is in Erase Suspend, but

cannot distinguish which sectors are selected for era-

sure. Thus, both status bits are required for sector and

mode information. Refer to Table 5 to compare outputs

for DQ2 and DQ6.

Figure 4 shows the toggle bit algorithm in flowchart

form, and the section “DQ2: Toggle Bit II” explains the

algorithm. See also the “DQ6: Toggle Bit I” subsection.

Refer to the Toggle Bit Timings figure for the toggle bit

timing diagram. The DQ2 vs. DQ6 figure shows the dif-

ferences between DQ2 and DQ6 in graphical form.

Reading Toggle Bits DQ6/DQ2

Refer to Figure 4 for the following discussion. When-

ever the system initially begins reading toggle bit

status, it must read DQ7–DQ0 at least twice in a row to

determine whether a toggle bit is toggling. Typically, a

system would note and store the value of the toggle bit

after the first read. After the second read, the system

would compare the new value of the toggle bit with the

first. If the toggle bit is not toggling, the device has com-

pleted the program or erase operation. The system can

read array data on DQ7–DQ0 on the following read

cycle.

However, if after the initial two read cycles, the system

determines that the toggle bit is still toggling, the sys-

tem also should note whether the value of DQ5 is high

(see the section on DQ5). If it is, the system should

then determine again whether the toggle bit is toggling,

since the toggle bit may have stopped toggling just as

DQ5 went high. If the toggle bit is no longer toggling,

the device has successfully completed the program or

erase operation. If it is still toggling, the device did not

complete the operation successfully, and the system

must write the reset command to return to reading

array data.

The remaining scenario is that the system initially de-

termines that the toggle bit is toggling and DQ5 has not

gone high. The system may continue to monitor the

toggle bit and DQ5 through successive read cycles, de-

termining the status as described in the previous

paragraph. Alternatively, it may choose to perform

other system tasks. In this case, the system must start

at the beginning of the algorithm when it returns to de-

termine the status of the operation (top of Figure 4).

DQ5: Exceeded Timing Limits

DQ5 indicates whether the program or erase time has

exceeded a specified internal pulse count limit. Under

these conditions DQ5 produces a “1.” This is a failure

condition that indicates the program or erase cycle was

not successfully completed.

March 3, 2009 21445E6

Am29F040B

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