ADV7301A View Datasheet(PDF) - Analog Devices

Part Name

Description

Manufacturer

ADV7301A

Multiformat SD, Progressive Scan/HDTV Video Encoder with Six NSV™ 12-Bit DACs

Analog Devices 

ADV7300A/ADV7301A

TIMING SPECIFICATIONS (VAA = VDD = 2.375 V–2.625 V, VDD_IO = 2.375 V–3.600 V, VREF = 1.235 V, RSET = 760 ⍀, RLOAD = 150 ⍀,

TMIN to TMAX (0؇C to 70؇C), unless otherwise noted.)

Parameter

Min

Typ

Max

Unit

Test Conditions

MPU PORT1

SCLOCK Frequency

0

SCLOCK High Pulsewidth, t1

0.6

SCLOCK Low Pulsewidth, t2

1.3

Hold Time (Start Condition), t3

0.6

Setup Time (Start Condition), t4

0.6

Data Setup Time, t5

100

SDATA, SCLOCK Rise Time, t6

SDATA, SCLOCK Fall Time, t7

Setup Time (Stop Condition), t8

0.6

RESET Low Time

100

400

kHz

µs

µs

µs

µs

ns

300

ns

300

ns

µs

ns

First Clock Generated after

This Period

Relevant for Repeated Start

Condition

ANALOG OUTPUTS

Analog Output Delay2

Output Skew

8

ns

1

ns

CLOCK CONTROL AND PIXEL PORT3

fCLK

fCLK

Clock High Time, t9

40

Clock Low Time, t10

40

Data Setup Time, t11

2.0

Data Hold Time, t12

2.0

Output Access Time, t13

Output Hold Time, t14

4.0

Pipeline Delay

27

81

14

61

62.5

66.5

33

43.5

36

MHz

MHz

% 1 clkcycle

% 1 clkcycle

ns

ns

ns

ns

clkcycles

clkcycles

clkcycles

clkcycles

clkcycles

clkcycles

Progressive Scan Mode

HDTV Mode/Async Mode

SD [2ϫ]

SD [8ϫ]

SD Component Filter [8ϫ]

PS [1ϫ], HD [1ϫ], Async

Timing Mode

PS [4ϫ]

HD [2ϫ]

NOTES

1Guaranteed by characterization.

2Output delay measured from the 50% point of the rising edge of CLOCK to the 50% point of DAC output full-scale transition.

3Data: C[9:0]; S[9:0]; Y[9:0]

Control: P_HSYNC; P_ VSYNC; P_BLANK; S_HSYNC; S_VSYNC; S_BLANK

Specifications subject to change without notice.

REV. A

–5–

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