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ADV7120KPZ30 查看數據表(PDF) - Analog Devices

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ADV7120KPZ30 CMOS 80 MHz, Triple 8-Bit Video DAC ADI
Analog Devices ADI
ADV7120KPZ30 Datasheet PDF : 12 Pages
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ADV7120
A resistance RSET connected between FS ADJUST and GND
determines the amplitude of the output video level according to
the following equations:
IOG (mA) = 12,082 × VREF (V)/RSET ()
(1)
IOR, IOB (mA) = 8,628 × VREF (V)/RSET ()
(2)
If SYNC is not being encoded onto the green channel, then
Equation 1 will be similar to Equation 2.
Using a variable value of RSET, as shown in Figure 4, allows for
accurate adjustment of the analog output video levels. Use of a
fixed 560 RSET resistor yields the analog output levels as
quoted in the specification page. These values also correspond
to the RS-343A video waveform values as shown in Figure 3.
COMP
ANALOG POWER PLANE
0.1µF
+5V
VAA
TO DACs
1k
VREF
IREF 4mA
FS ADJUST
ADV7120*
RSET
560
GND
500
100
AD589
(1.235V
VOLTAGE
REFERENCE)
as a doubly terminated 75 coaxial cable. Figure 5a shows the
required configuration for each of the three RGB outputs con-
nected into a doubly terminated 75 load. This arrangement
will develop RS-343A video output voltage levels across a 75
monitor.
DACs
IOR, IOG, IOB
ZS = 75
(SOURCE
TERMINATION)
ZO = 75
(CABLE)
ZL = 75
(MONITOR)
TERMINATION REPEATED THREE TIMES
FOR RED, GREEN AND BLUE DACs
Figure 5a. Analog Output Termination for RS-343A
One suggested method of driving RS-170 video levels into a 75
monitor is shown in Figure 5b. The output current levels of the
DACs remain unchanged but the source termination resistance,
ZS, on each of the three DACs is increased from 75 to 150 .
IOR, IOG, IOB
ZO = 75
DACs
ZS = 150
(SOURCE
TERMINATION)
(CABLE)
ZL = 75
(MONITOR)
*ADDITIONAL CIRCUITRY, INCLUDING
DECOUPLING COMPONENTS,
EXCLUDED FOR CLARITY
Figure 4. Reference Circuit
D/A Converters
The ADV7120 contains three matched 8-bit D/A converters.
The DACs are designed using an advanced, high speed, seg-
mented architecture. The bit currents corresponding to each
digital input are routed to either the analog output (bit = “1”)
or GND (bit = “0”) by a sophisticated decoding scheme. As all
this circuitry is on one monolithic device, matching between the
three DACs is optimized. As well as matching, the use of identi-
cal current sources in a monolithic design guarantees monoto-
nicity and low glitch. The onboard operational amplifier
stabilizes the full-scale output current against temperature and
power supply variations.
Analog Outputs
The ADV7120 has three analog outputs, corresponding to the red,
green and blue video signals. A fourth analog output (ISYNC) can be
used if it is required to encode video synchronization information
onto the green signal. In this case, ISYNC is connected to IOG .
(See “Video Synchronization and Control” section.)
The red, green and blue analog outputs of the ADV7102 are
high impedance current sources. Each one of these three RGB
current outputs is capable of directly driving a 37.5 load, such
TERMINATION REPEATED THREE TIMES
FOR RED, GREEN AND BLUE DACs
Figure 5b. Analog Output Termination for RS-170
More detailed information regarding load terminations for vari-
ous output configurations, including RS-343A and RS-170, is
available in an application note entitled “Video Formats & Re-
quired Load Terminations” available from Analog Devices,
publication number E1228-15-1/89.
Figure 3 shows the video waveforms associated with the three
RGB outputs driving the doubly terminated 75 load of Figure
5a. As well as the gray scale levels, black level to white level, the
diagram also shows the contributions of SYNC and BLANK.
These control inputs add appropriately weighted currents to the
analog outputs, producing the specific output level requirements
for video applications. Table I details how the SYNC and
BLANK inputs modify the output levels.
Gray Scale Operation
The ADV7120 can be used for stand-alone, gray scale (mono-
chrome) or composite video applications (i.e., only one channel
used for video information). Any one of the three channels, red,
green or blue, can be used to input the digital video data. The
two unused video data channels should be tied to logical zero.
–8–
REV. B
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