If we, therefore, have a graphics system with a 1024 × 1024
resolution, a noninterlaced 60 Hz refresh rate and a retrace fac-
tor of 0.8, then:
Dot Rate = 1024 × 1024 × 60/0.8
= 78.6 MHz
19.05 0.714 26.67 1.000
The required CLOCK frequency is thus 78.6 MHz.
All video data and control inputs are latched into the ADV7120
on the rising edge of CLOCK, as previously described in the
“Digital Inputs” section. It is recommended that the CLOCK
input to the ADV7120 be driven by a TTL buffer (e.g.,
1.44 0.054 9.05 0.340
0 7.62 0.286
1. OUTPUTS CONNECTED TO A DOUBLY TERMINATED 75Ω LOAD.
2. VREF = 1.235V, RSET = 560Ω, ISYNC CONNECTED TO IOG.
3. RS-343A LEVELS AND TOLERANCES ASSUMED ON ALL LEVELS.
Figure 3. RGB Video Output Waveform
Table I. Video Output Truth Table
video + 9.05 video + 1.44 0
VIDEO to BLANK video + 1.44 video + 1.44 0
BLACK to BLANK 1.44
Typical with full-scale IOG = 26.67 mA.
VREF = 1.235 V, RSET = 560 Ω, ISYNC connected to IOG.
BLANK Input Data
Video Synchronization and Control
The ADV7120 has a single composite video sync (SYNC) input
control. Many graphics processors and CRT controllers have
the ability of generating horizontal sync (HSYNC), vertical sync
(VSYNC) and composite SYNC.
In a graphics system which does not automatically generate a
composite SYNC signal, the inclusion of some additional logic
circuitry will enable the generation of a composite SYNC signal.
The ISYNC current output is typically connected directly to the
IOG output, thus encoding video synchronization information
onto the green video channel. If it is not required to encode sync
information onto the ADV7120’s analog outputs, the SYNC in-
put should be tied to logic low and the ISYNC should be con-
nected to analog ground.
An external 1.23 V voltage reference is required to drive
the ADV7120. The AD589 from Analog Devices is an
ideal choice of reference. It is a two-terminal, low cost,
temperature compensated bandgap voltage reference which
provides a fixed 1.23 V output voltage for input currents
between 50 µA and 5 mA. Figure 4 shows a typical refer-
ence circuit connection diagram. The voltage reference gets
its current drive from the ADV7120’s VAA through an on-
board 1 kΩ resistor to the VREF pin. A 0.1 µF ceramic ca-
pacitor is required between the COMP pin and VAA.
This is necessary so as to provide compensation for the
internal reference amplifier.