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ADV7120KPZ30 查看數據表(PDF) - Analog Devices

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ADV7120KPZ30 CMOS 80 MHz, Triple 8-Bit Video DAC ADI
Analog Devices ADI
ADV7120KPZ30 Datasheet PDF : 12 Pages
1 2 3 4 5 6 7 8 9 10 Next Last
Pin
Mnemonic
BLANK
SYNC
CLOCK
REF WHITE
R0–R7,
G0–G7,
B0–B7
IOR, IOG, IOB
ISYNC
FS ADJUST
COMP
VREF
VAA
GND
PIN FUNCTION DESCRIPTION
ADV7120
Function
Composite blank control input (TTL compatible). A logic zero on this control input drives the analog out-
puts, IOR, IOB and IOG, to the blanking level. The BLANK signal is latched on the rising edge of CLOCK.
While BLANK is a logical zero, the R0–R7, G0–G7, R0–R7 and REF WHITE pixel and control inputs are
ignored.
Composite sync control input (TTL compatible). A logical zero on the SYNC input switches off a 40 IRE
current source on the ISYNC output. SYNC does not override any other control or data input; therefore, it
should only be asserted during the blanking interval. SYNC is latched on the rising edge of CLOCK.
Clock input (TTL compatible). The rising edge of CLOCK latches the R0–R7, G0–G7, B0–B7, SYNC,
BLANK and REF WHITE pixel and control inputs. It is typically the pixel clock rate of the video system.
CLOCK should be driven by a dedicated TTL buffer.
Reference white control input (TTL compatible). A logical one on this input forces the IOR, IOG and IOB
outputs to the white level, regardless of the pixel input data (R0–R7, G0–G7 and B0–B7). REF WHITE is
latched on the rising edge of clock.
Red, green and blue pixel data inputs (TTL compatible). Pixel data is latched on the rising edge of CLOCK.
R0, G0 and B0 are the least significant data bits. Unused pixel data inputs should be connected to either the
regular PCB power or ground plane.
Red, green, and blue current outputs. These high impedance current sources are capable of directly driving
a doubly terminated 75 coaxial cable. All three current outputs should have similar output loads whether
or not they are all being used.
Sync current output. This high impedance current source can be directly connected to the IOG output. This
allows sync information to be encoded onto the green channel. ISYNC does not output any current while
SYNC is at logical zero. The amount of current output at ISYNC while SYNC is at logical one is given by:
ISYNC (mA) = 3,455 × VREF (V)/ RSET ()
If sync information is not required on the green channel, ISYNC should be connected to AGND.
Full-scale adjust control. A resistor (RSET) connected between this pin and GND, controls the magnitude of
the full-scale video signal. Note that the IRE relationships are maintained, regardless of the full-scale output
current.
The relationship between RSET and the full-scale output current on IOG (assuming ISYNC is connected to
IOG) is given by:
RSET () = 12,082 × VREF (V)/IOG (mA)
The relationship between RSET and the full-scale output current on IOR and IOB is given by:
IOR, IOB (mA) = 8,628 × VREF (V)/ RSET ()
Compensation pin. This is a compensation pin for the internal reference amplifier. A 0.1 µF ceramic capaci-
tor must be connected between COMP and VAA.
Voltage reference input. An external 1.2 V voltage reference must be connected to this pin. The use of an ex-
ternal resistor divider network is not recommended. A 0.1 µF decoupling ceramic capacitor should be con-
nected between VREF and VAA.
Analog power supply (5 V ± 5%). All VAA pins on the ADV7120 must be connected.
Ground. All GND pins must be connected.
REV. B
–5–
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