ADV7120KST30 View Datasheet(PDF) - Analog Devices
Part Name
Description
Manufacturer
ADV7120KST30 Datasheet PDF : 12 Pages
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ADV7120
TIMING CHARACTERISTICS1 (VAA = +5 V ؎ 5%; VREF = +1.235 V; RL = 37.5 ⍀, CL = 10 pF; RSET = 560 ⍀.
ISYNC connected to IOG. All Specifications TMIN to TMAX2 unless otherwise noted.)
Parameter 80 MHz Version 50 MHz Version 30 MHz Version Units
Conditions/Comments
fMAX
80
50
30
MHz max Clock Rate
tl
3
6
8
ns min
Data & Control Setup Time
t2
2
2
2
ns min
Data & Control Hold Time
t3
12.5
20
33.3
ns min
Clock Cycle Time
t4
4
7
9
ns min
Clock Pulse Width High Time
t5
4
7
9
ns min
Clock Pulse Width Low Time
t6
30
30
30
ns max
Analog Output Delay
20
20
20
ns typ
t7
3
3
3
t83
12
15
15
ns max
ns typ
Analog Output Rise/Fall Time
Analog Output Transition Time
NOTES
1TTL input values are 0 to 3 volts, with input rise/fall times ≤3 ns, measured between the 10% and 90% points. Timing reference points at 50% for inputs
and outputs. See timing notes in Figure 1.
2Temperature range (TMIN to TMAX): 0°C to +70°C
3Sample tested at +25°C to ensure compliance.
Specifications subject to change without notice.
t4
t5
CLOCK
t3
DIGITAL INPUTS
(R0-R7, G0-G7, B0-B7;
SYNC, BLANK,
REF WHITE)
ANALOG OUTPUTS
(IOR, IOG, IOB, ISYNC )
t2
t1
DATA
t6
t8
t7
NOTES
1. OUTPUT DELAY (t6) MEASURED FROM THE 50% POINT OF THE RISING EDGE OF
CLOCK TO THE 50% POINT OF FULL-SCALE TRANSITION.
2. TRANSITION TIME (t8) MEASURED FROM THE 50% POINT OF FULL-SCALE
TRANSITION TO WITHIN 2% OF THE FINAL OUTPUT VALUE.
3. OUTPUT RISE/FALL TIME (t7) MEASURED BETWEEN THE 10% AND 90% POINTS
OF FULL TRANSITION.
Figure 1. Video Input/Output Timing
REV. B
–3–
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