ADP667 View Datasheet(PDF) - Analog Devices
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ADP667 Datasheet PDF : 12 Pages
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ADP667
POWER DISSIPATION
The ADP667 can supply currents up to 250 mA and can oper-
ate with input voltages as high as 16.5 V, but not simultaneously.
It is important that the power dissipation and hence the internal
die temperature be maintained below the maximum limits. Power
Dissipation is the product of the voltage differential across the
regulator times the current being supplied to the load. The
maximum package power dissipation is given in the Absolute
Maximum Ratings. In order to avoid excessive die temperatures,
these ratings must be strictly observed.
PD = (VIN – VOUT ) (IL )
The die temperature is dependent on both the ambient tempera-
ture and on the power being dissipated by the device. The inter-
nal die temperature must not exceed 125°C. Therefore, care
must be taken to ensure that, under normal operating condi-
tions, the die temperature is kept below the thermal limit.
TJ = TA + PD (θJA)
This may be expressed in terms of power dissipation as follows:
where:
PD = (TJ – TA)/(θJA)
TJ = Die Junction Temperature (°C)
TA = Ambient Temperature (°C)
PD = Power Dissipation (W)
θJA = Junction to Ambient Thermal Resistance (°C/W)
If the device is being operated at the maximum permitted ambi-
ent temperature of 85°C, the maximum power dissipation per-
mitted is:
where:
PD (max) = (TJ (max) – TA)/(θJA)
PD (max) = (125 – 85)/(θJA)
= 40/θJA
θJA = 120°C/W for the 8-pin DIP (N-8) package
θJA = 170°C/W for the 8-pin SOIC (SO-8) package
Therefore, for a maximum ambient temperature of 85°C:
PD (max) = 333 mW for N-8
PD (max) = 235 mW for SO-8
At lower ambient temperatures the maximum permitted power
dissipation increases accordingly up to the maximum limits
specified in the absolute maximum specifications.
The thermal impedance (θJA) figures given are measured in still
air conditions and are reduced considerably where fan assisted
cooling is employed. Other techniques for reducing the thermal
impedance include large contact pads on the printed circuit
board and wide traces. The copper will act as a heat exchanger
thereby reducing the effective thermal impedance.
High Power Dissipation Recommendations
Where excessive power dissipation due to high input-output
differential voltages and/or high current conditions exists, the
simplest method of reducing the power requirements on the
regulator is to use a series dropper resistor. In this way the
excess power can be dissipated in the external resistor. As an
example, consider an input voltage of +12 V and an output
voltage requirement of +5 V @ 100 mA with an ambient tem-
perature of +85°C. The package power dissipation under these
conditions is 700 mW which exceeds the maximum ratings. By
using a dropper resistor to drop 4 V, the power dissipation
requirement for the regulator is reduced to 300 mW which is
within the maximum specifications for the N-8 package at 85°C.
The resistor value is calculated as R = 4/0.1 = 40 Ω. A resistor
power rating of 400 mW or greater may be used.
40Ω
VIN
12V
0.5W
C1
1µF
IN
+
OUT
ADP667
+ C2
10µF
+5V
OUTPUT
SET GND SHDN
Figure 14. Reducing Regulator Power Dissipation
Transient Response
The ADP667 exhibits excellent transient performance as illus-
trated in the “Typical Performance Characteristics.” Figure 12
shows that an input step from 10 V to 6 V results in a very small
output disturbance (50 mV). Adding an input capacitor would
improve this even more.
Figure 13 shows how quickly the regulator recovers from an
output load change from 10 mA to 100 mA. The offset due to
the load current change is less than 1 mV.
Monitored µP Power Supply
Figure 15 shows the ADP667 being used in a monitored µP
supply application. The ADP667 supplies +5 V for the micro-
processor. Monitoring the supply, the ADM705 will generate a
reset if the supply voltage falls below 4.65 V. Early warning of
an impending power fail is generated by a power fail comparator
on the ADM705. A resistive divider network samples the pre-
regulator input voltage so that failing power is detected while
the regulator is still operating normally. An interrupt is gener-
ated so that a power-down sequence can be completed before
power is completely lost. The low dropout voltage on the
ADP667 maximizes the available time to carry out the power-
down sequence. The resistor divider network R1 and R2 should
be selected so that the voltage on PFI is 1.25 V at the desired
warning voltage.
UNREGULATED
DC
IN
ADP667
OUT
GND SET SHDN
+5V
+
10µF
VCC
RESET
R1
ADM705
PFI
R2
PFO
GND
VCC
RESET
µP
INTERRUPT
Figure 15. µP Regulator with Supply Monitoring and Early
Power-Fail Warning
REV. A0
–7–
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