ADP667 View Datasheet(PDF) - Analog Devices
Part Name
Description
Manufacturer
ADP667 Datasheet PDF : 12 Pages
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ADP667
PIN FUNCTION DESCRIPTION
Mnemonic Function
DD
VIN
GND
LBI
LBO
SHDN
SET
OUT
Dropout Detector Output. PNP collector output
which sources current as dropout is reached.
Voltage Regulator Input.
Ground Pin. Must be connected to 0 V.
Low Battery Detect Input. Compared with 1.255 V.
Low Battery Detect Output. Open Drain Output
that goes low when LBI is below the threshold.
Digital Input. May be used to disable the device
so that the power consumption is minimized.
Voltage Setting Input. Connect to GND for +5 V
output or connect to resistive divider for adjust-
able output.
Regulated Output Voltage. Connect to filter
capacitor.
DIP & SOIC PIN CONFIGURATION
DD 1
8 IN
OUT
LBI
GND
2 ADP667
3
TOP VIEW
(Not to Scale)
4
7 LBO
6 SET
5 SHDN
TERMINOLOGY
Dropout Voltage: The input/output voltage differential at
which the regulator no longer maintains regulation against fur-
ther reductions in input voltage. It is measured when the output
decreases 100 mV from its nominal value. The nominal value is
the measured value with VIN = VOUT +2 V.
Line Regulation: The change in output voltage as a result of a
change in the input voltage. It is specified for a change of input
voltage from 6 V to 10 V.
Load Regulation: The change in output voltage for a change
in output current. It is specified for an output current change
from 10 mA to 200 mA.
Quiescent Current (IGND): The input bias current which
flows into the regulator not including load current. It is mea-
sured on the GND line and is specified in shutdown and also for
different values of load current.
Shutdown: The regulator is disabled and power consumption
is minimized.
Dropout Detector: An output that indicates that the regulator
is dropping out of regulation.
Maximum Power Dissipation: The maximum total device
dissipation for which the regulator will continue to operate
within specifications.
GENERAL INFORMATION
The ADP667 contains a micropower bandgap reference voltage
source, an error amplifier A1, two comparators (C1, C2) and a
series PNP output pass transistor.
CIRCUIT DESCRIPTION
The internal bandgap voltage reference is trimmed to 1.255 V
and is used as a reference input to the error amplifier A1. The
feedback signal from the regulator output is supplied to the
other input by an on-chip voltage divider or by two external
resistors. When the SET input is at ground, the internal divider
provides the error amplifier’s feedback signal giving a +5 V out-
put. When SET is at more than 50 mV above ground, compara-
tor C1 switches the error amplifier’s input directly to the SET
pin, and external resistors are used to set the output voltage.
The external resistors are selected so that the desired output
voltage gives 1.255 V at the SET input.
The output from the error amplifier supplies base current to the
PNP output pass transistor which provides output current. Up
to 250 mA output current is available provided that the device
power dissipation is not exceeded.
Comparator C2 compares the voltage on the Low Battery Input,
LBI, pin to the internal +1.255 V reference voltage. The output
from the comparator drives an open drain FET connected to the
Low Battery Output pin, LBO. The Low Battery Threshold
may be set using a suitable voltage divider connected to LBI.
When the voltage on LBI falls below 1.255 V, the open drain
output, LBO, is pulled low.
A shutdown (SHDN) input that can be used to disable the
error amplifier and hence the voltage output is also available.
The supply current in shutdown is less than 1 µA.
IN
OUT
ADP667
DD
SHDN
LBO
LBI
GND
A1
C2
1.255V
REF
SET
C1
50mV
Figure 1. ADP667 Functional Block Diagram
REV. A0
–3–
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