DatasheetQ Logo
Electronic component search and free download site.
Transistors,MosFET ,Diode,Integrated circuits

MTV021N20 View Datasheet(PDF) - Myson Century Inc

Part Name
Description
Manufacturer
MTV021N20
Myson
Myson Century Inc Myson
MTV021N20 Datasheet PDF : 17 Pages
1 2 3 4 5 6 7 8 9 10 Next Last
MYSON
TECHNOLOGY
MTV021
TABLE 2. Repeat line weight of character
CH6 - CH0
CH3=1
CH2=1
CH1=1
CH0=1
Repeat Line Weight
+8
+4
+2
+1
TABLE 3. Repeat line number of character
Repeat Line
Repeat Line #
Weight
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17
+1
- - - - - - - -v- - - - - - - - -
+2
- - - -v- - - - - - -v- - - - -
+4
- -v- - -v- - -v- - -v- - -
+8
-v-v-v-v-v-v-v-v- -
+16
- vvvvvvvvvvvvvvvv -
+17
vvvvvvvvvvvvvvvvv -
+18
vvvvvvvvvvvvvvvvvv
Note:" v " means the nth line in the character would be repeated once, while " - " means the nth line in the
character would not be repeated.
3.4 Horizontal display control
The horizontal display control is used to generate control timing for horizontal display based on double char-
acter width bit (CWS), horizontal positioning register (HORD), horizontal resolution register (HORR), and
HFLB input. A horizontal display line consists of (HORR*12) dots which include 360 dots for 30 display char-
acters and the remaining dots for blank region. The horizontal delay starting from HFLB leading edge is calcu-
lated with the following equation,
Horizontal delay time = ( HORD * 6 + 49) * P - phase error detection pulse width
Where P = One pixel display time = One horizontal line display time / (HORR*12)
3.5 Phase lock loop (PLL)
On-chip PLL generates system clock timing (VCLK) by tracking the input HFLB and horizontal resolution reg-
ister (HORR). The frequency of VCLK is determined by the following equation:
VCLK Freq = HFLB Freq * HORR * 12
The VCLK frequency ranges from 6MHz to 96MHz selected by (VCO1, VCO0). In addition, when HFLB input
is not present to MTV021, the PLL will generate a specific system clock, approximately 2.5MHz, by a built-in
oscillator to ensure data integrity.
3.6 Display & Row control registers
The internal RAM contains display and row control registers. The display registers have 450 locations which
are allocated between (row 0, column 0) to (row 14, column 29), as shown in Figure 4. Each display register
has its corresponding character address on ADDRESS byte, its corresponding background color, 1 blink bit
and its corresponding color bits on ATTRIBUTE bytes. The row control register is allocated at column 30 for
6/17
MTV021 Revision 5.0 6/29/1999
 

Share Link: 

datasheetq.com  [ Privacy Policy ]Request Datasheet ] [ Contact Us ]