UT69151-XTE5WCX View Datasheet(PDF) - Aeroflex UTMC
Part Name
Description
Manufacturer
UT69151-XTE5WCX Datasheet PDF : 177 Pages
| |||
2.1.2 Operational Status Register (Read/Write) - Register 1
This register reflects pertinent status information for the SRT and is not reset to 0000 (hex) on MRST. Instead, the register reflects
the actual stimulus applied to input pins RTA(4:0), RTPTY, MSEL(1:0), A/B STD, and LOCK. Assertion of the LOCK input prevents
the modification of the remote terminal address, mode selects, and A or B Standard. In this case, a write to this register’s most
significant nine bits is meaningless. If LOCK is negated, a read of this register reflects the information written into this register’s
most significant nine bits.
Note: To make changes to the SRT and this register, the STEX bit (Bit 15 in Register 0) must be logic zero.
Bit
Number
Mnemonic
Description
15
RTA4
Terminal Address Bit 4. This bit is the most significant bit of the remote terminal address.
This bit is latched on the rising edge of MRST and is a read only bit if the LOCK pin is
active.
14
RTA3
Terminal Address Bit 3. This bit is Bit 3 of the remote terminal address. This bit is latched
on the rising edge of MRST and is a read only bit if the LOCK pin is active.
13
RTA2
Terminal Address Bit 2. This bit is Bit 2 of the remote terminal address. This bit is latched
on the rising edge of MRST and is a read only bit if the LOCK pin is active.
12
RTA1
Terminal Address Bit 1. This bit is Bit 1 of the remote terminal address. This bit is latched
on the rising edge of MRST and is a read only bit if the LOCK pin is active.
11
RTA0
Terminal Address Bit 0. This bit is the least significant bit of the remote terminal address.
This bit is latched on the rising edge of MRST and is a read only bit if the LOCK pin is
active.
10
RTPTY
Terminal Address Parity Bit. This bit is appended to the remote terminal address bus
(RTA(4:0)) to supply odd parity. The SRT requires odd parity for proper operation. This
bit is latched on the rising edge of MRST and is a read only bit if the LOCK pin is active.
9
MSEL(1)
Mode Select 1. In conjunction with MSEL0, this bit determines the SµΜΜIT mode of
operation. This bit is latched on the rising edge of MRST and is a read only bit if the
LOCK pin is active.
8
MSEL(0)
Mode Select 0. In conjunction with MSEL1, this bit determines the SµΜΜIT mode of
operation. This bit is latched on the rising edge of MRST and is a read only bit if the
LOCK pin is active.
MSEL(1)
MSEL(0)
Mode of Operation
0
0
SBC
0
1
SRT
1
0
SMT
1
1
SMT/SRT
7
A/B STD
Military Standard 1553A or 1553B Standard. This bit determines whether the SRT will
be set to operate under MIL-STD-1553A or B. Assertion of this bit enables the XMTSW
bit (Bit 0 of the Control Register). Negation of this bit automatically allows the SRT to
operate under the MIL-STD-1553B protocol. This bit is latched on the rising edge of
MRST and is a read only bit if the LOCK pin is active. See section 2.9 for further definition.
6
LOCK
LOCK Pin. This read-only bit reflects the inverted state of input pin LOCK and is latched
on the rising edge of MRST.
5
AUTOEN
AUTOEN Pin. This read-only bit reflects the inverted state of input pin AUTOEN.
Assertion of this input enables SRT auto-initialization.
4
SSYSF
SSYSF Pin. This read-only bit reflects the inverted state of the input pin SSYSF.
8
SµMMIT FAMILY
|
|
Share Link: 