ADC0820 View Datasheet(PDF) - Philips Electronics
Part Name
Description
Manufacturer
ADC0820 Datasheet PDF : 14 Pages
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Philips Semiconductors Linear Products
8-Bit, high-speed, µP-compatible A/D converter with
track/hold function
Product specification
ADC0820
To start a conversion in the WR-RD mode, the WR line is brought
Low. At this instant the MS comparators go from zeroing to
comparison mode (Figure 8). When WR is returned High after at
least 600ns, the output from the first set of comparators (the first
flash) is decoded and latched. At this point the two 4-bit converters
change modes and the LS (least significant) flash ADC enters its
compare cycle. No less than 600ns later, the RD line may be pulled
Low to latch the lower four data bits and finish the 8-bit conversion.
When RD goes Low, the flash A/Ds change state once again in
preparation for the next conversion.
Figure 8 also outlines how the converter’s interface timing relates to
its analog input (VIN). In WR-RD mode, VIN is measured while WR is
Low. In RD mode, sampling occurs during the first 800ns of RD.
Because of the input connections to the ADC0820’s LS and MS
comparators, the converter has the ability to sample VIN at one
instant, despite the fact that two separate 4-bit conversions are
being done. More specifically, when WR is Low the MS flash is in
compare mode (connected to VIN, and the LS flash is in zero mode
(also connected to VIN). Therefore both flash ADCs sample VIN at
the same time.
Digital Interface
The ADC0820 has two basic interface modes which are selected by
strapping the Mode pin High or Low.
RD Mode (Figure 6a)
With the Mode pin grounded, the converter is set to Read mode. In
this configuration, a complete conversion is done by pulling RD Low
until output data appears. An INT line is provided which goes Low at
the end of the conversion as well as a RDY output which can be
used to signal a processor that the converter is busy or can also
serve as a system Transfer Acknowledge signal.
When in RD mode, the comparator phases are internally triggered.
At the falling edge of RD, the MS flash converter goes from zero to
compare mode and the LS ADC’s comparators enter their zero
cycle. After 800ns, data from the MS flash is latched and the LS
flash ADC enters compare mode. Following another 800ns, the
lower four bits are recovered.
WR Then RD Mode (Figures 6b and c)
With the Mode pin tied High, the A/D will be set up for the WR-RD
mode. Here, a conversion is started with the WR input; however,
there are two options for reading the output data which relate to
interface timing. If an interrupt-driven scheme is desired, the user
can wait for INT to go Low
CS
RD
RDY
INT
DB0–DB7
a. RD Mode (Pin 7 is Low)
CS
WR
RB
INT
DB0–DB7
b. WR-RD Mode (Pin 7 is High and tRD < tI)
CS
WR
RB
INT
DB0–DB7
c. WR-RD Mode (Pin 7 is High and tRD > tI)
Figure 6.
August 31, 1994
576
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