ADC0820 View Datasheet(PDF) - Philips Electronics

Part Name

Description

Manufacturer

ADC0820

8-Bit, high-speed, µP-compatible A/D converter with track/hold function

Philips Electronics 

Philips Semiconductors Linear Products

8-Bit, high-speed, µP-compatible A/D converter with

track/hold function

BLOCK DIAGRAM

VIN

VREF(+)

VREF(–)

VREF(+)

+

–

∑

VREF(–)

V1R6EF(+)

VREF(–)

OFL

4–BIT

FLASG

ADC

(4MSBs)

4–BIT

DAC

OFL

DB7

DB6

DB5

DB4

OUTPUT

LATCH

AND

THREE–STATE

BUFFERS

4–BIT

FLASG

ADC

(4LSBs)

TIMING AND CONTROL CIRCUITRY

MODE WR/RDY

CS

RD

DB3

DB2

DB1

DB0

INT

Product specification

ADC0820

PIN DESCRIPTION

PIN NO SYMBOL

DESCRIPTION

1

VIN

2 DB0

Analog input; range=GND≤VIN≤VDD

3-state data output—Bit 0 (LSB)

3 DB1

3-state data output—Bit 1

4 DB2

3-state data output—Bit 2

5 DB3

3-state data output—Bit 3

6 WR/RDY WR-RD Mode

WR: With CS Low, the conversion is started on the falling edge of WR. Approximately 800ns (the preset internal time

out, tI) after the WR rising edge, the result of the conversion will be strobed into the output latch, provided that RD

does not occur prior to this time out (see Figures 3a and 3b).

RD Mode

RDY: This is an open-drain output (no internal pull-up device). RDY will go Low after the falling edge of CS; RDY will

go 3-State when the result of the conversion is strobed into the output latch. It is used to simplify the interface to a

microprocessor system (see Figure 1).

7 Mode

Mode: Mode selection input—it is internally tied to GND through a 30µA current source.

RD Mode: When mode is Low.

WR-RD Mode: When mode is High.

8 RD

WR-RD Mode

With CS Low, the 3-State data outputs (DB0-DB7) will be activated when RD goes Low. RD can also be used to

increase the speed of the converter by reading data prior to the preset internal time out (TI ~ 800ns). If this is done,

the data result transferred to output latch is latched after the falling edge of the RD (see Figures 3a and 3b).

RD Mode

With CS Low, the conversion will start with RD going Low; also, RD will enable the 3-State data outputs at the

completion of the conversion. RDY going 3-State and INT going Low indicate the completion of the conversion (see

Figure 1).

9 INT

WR-RD Mode

INT going Low indicates that the conversion is completed and the data result is in the output latch. INT will go

Low ~ 800ns (the preset internal time out, tI) after the rising edge of WR (see Figure 3a); or INT will go Low after

the falling edge of RD, if RD goes Low prior to the 800ns time out (see Figure 3b). INT is reset by the rising edge of

RD or CS (see Figures 3a and 3b).

August 31, 1994

569

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