AD9520-0 View Datasheet(PDF) - Analog Devices
Part Name
Description
Manufacturer
AD9520-0 Datasheet PDF : 84 Pages
| |||
–100
–110
–120
–130
–140
–150
–160
10
100
1k
10k 100k
1M
10M 100M
FREQUENCY (Hz)
Figure 30. Additive (Residual) Phase Noise, CLK-to-CMOS @
250 MHz, Divide-by-4
–100
–110
–120
–130
–140
–150
–160
1k
10k
100k
1M
10M
100M
FREQUENCY (Hz)
Figure 31. Phase Noise (Absolute) Clock Generation; Internal VCO @
2.703 GHz; PFD = 15.36 MHz; LBW = 63 kHz; LVPECL Output = 122.88 MHz
–80
INTEGRATED RMS JITTER (12kHz TO 20MHz): 652fs
–90
–100
–110
–120
–130
–140
–150
–160
1k
10k
100k
1M
10M
100M
FREQUENCY (Hz)
Figure 32. Phase Noise (Absolute) Clock Cleanup; Internal VCO @ 2.799 GHz;
PFD = 120 kHz; LBW = 2.1 kHz; LVPECL Output = 155.52 MHz
AD9520-0
–120
–130
–140
–150
–160
1k
10k
100k
1M
10M
100M
FREQUENCY (Hz)
Figure 33. Phase Noise (Absolute), External VCXO (Toyocom TCO-2112)
@ 245.76 MHz; PFD = 15.36 MHz; LBW = 250 Hz; LVPECL Output = 245.76 MHz
R2
390Ω
CP
LF
C1
C2
240nF
C3
62pF R1
33pF
820Ω
BYPASS
BYPASS
CAPACITOR
FOR LDO
C12
220nF
Figure 34. PLL Loop Filter Used for Clock Generation Plot (see Figure 31)
R2
3kΩ
CP
LF
C1
C2
4.7µF
C3
1.5nF R1
2.2nF
2.1kΩ
BYPASS
BYPASS
CAPACITOR
FOR LDO
C12
220nF
Figure 35. PLL Loop Filter Used for Clock Cleanup Plot (see Figure 32)
Rev. 0 | Page 25 of 84
|
|
Share Link: 