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ACE24C128DP-UH Просмотр технического описания (PDF) - ACE Technology Co., LTD.

Номер в каталогеACE24C128DP-UH ACE
ACE Technology Co., LTD. ACE
Компоненты ОписаниеTwo-wire Serial EEPROM

ACE24C128DP-UH Datasheet PDF : 18 Pages
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Two-wire Serial EEPROM
Device Operation
Clock and Data Transitions:
The SDA pin is normally pulled high with an external device. Data on the SDA pin may change only
during SCL low time periods (refer to Figure 4). Data changes during SCL high periods will indicate a
start or stop condition as defined below.
Start Condition:
A high-to-low transition of SDA with SCL high is a start condition which must precede any other
command (refer to Figure 5).
Stop Condition:
A low-to-high transition of SDA with SCL high is a stop condition. After a read sequence, the stop command
will place the EEPROM in a standby power mode (refer to Figure 5).
All addresses and data words are serially transmitted to and from the EEPROM in 8-bit words. The
EEPROM sends a zero during the ninth clock cycle to acknowledge that it has received each word.
Standby Mode :
The ACE24C128/256 features a low-power standby mode which is enabled: (a) upon power-up and (b)
after the receipt of the stop bit and the completion of any internal operations.
Memory Reset :
After an interruption in protocol power loss or system reset, any two-wire part can be protocol reset by following
these steps:
1. Clock up to 9 cycles.
2. Look for SDA high in each cycle while SCL is high and then.
3. Create a start condition as SDA is high.
Bus Timing
Figure 2.SCL: Serial Clock, SDA: Serial Data I/O
VER 1.5 7
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The ACE24C128/256 provides 131,072/262,144 bits of serial electrically erasable and programmable read-only memory (EEPROM) organized as16,384/32,768 words of 8 bits each. The device’s cascadable feature allows up to 8 devices to share a common two-wire bus. The device is optimized for use in many industrial and commercial applications where low-power and low-voltage operations are essential.

● Low Operation Voltage: Vcc = 1.7V to 5.5V
● Internally Organized: 16,384 x 8(128K), 32,768 x 8(256K)
● Two-wire Serial Interface
● Schmitt Trigger, Filtered Inputs for Noise Suppression
● Bi-directional Data Transfer Protocol
● 1MHz (2.5V~5.5V) and 400 kHz (1.7V) Compatibility
● Write Protect Pin for Hardware Data Protection
● 64-byte Page Write Modes (Partial Page Writes are Allowed)
● Self-timed Write Cycle (5 ms max)
● High-reliability - Endurance: 1,000,000 Write Cycles
                        - Data Retention: 40 Years


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