A290021U-70 View Datasheet(PDF) - AMIC Technology
Part Name
Description
Manufacturer
A290021U-70 Datasheet PDF : 32 Pages
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A29002/A290021 Series
Timing Waveforms for Alternate CE Controlled Write Operation (RESET =VIH on A29002)
555 for program
2AA for erase
PA for program
SA for sector erase
555 for chip erase
Data Polling
Addresses
PA
tWC
tAS
tWH
tAH
WE
tGHEL
OE
tCP
tWHWH1 or 2
CE
tWS
Data
tCPH
tDS
tDH
tBUSY
I/O7
DOUT
tRH
A0 for program
55 for erase
PD for program
30 for sector erase
10 for chip erase
Note :
1. PA = Program Address, PD = Program Data, SA = Sector Address, I/O 7 = Complement of Data Input, D OUT = Array Data.
2. Figure indicates the last two bus cycles of the command sequence.
Erase and Programming Performance
Parameter
Sector Erase Time
Chip Erase Time
Typ. (Note 1)
1
8
Max. (Note 2)
8
64
Unit
Comments
sec
Excludes 00h programming
sec
prior to erasure (Note 4)
Byte Programming Time
7
Chip Programming Time (Note 3)
3.6
300
µs
Excludes system-level
10.8
sec
overhead (Note 5)
Notes:
1. Typical program and erase times assume the following conditions: 25°C, 5.0V VCC, 100,000 cycles. Additionally,
programming typically assumes checkerboard pattern.
2. Under worst case conditions of 90°C, VCC = 4.5V (4.75V for -55), 100,000 cycles.
3. The typical chip programming time is considerably less than the maximum chip programming time listed, since most
bytes program faster than the maximum byte program time listed. If the maximum byte program time given is exceeded,
only then does the device set I/O5 = 1. See the section on I/O5 for further information.
4. In the pre-programming step of the Embedded Erase algorithm, all bytes are programmed to 00h before erasure.
5. System-level overhead is the time required to execute the four-bus-cycle command sequence for programming. See
Table 4 for further information on command definitions.
6. The device has a guaranteed minimum erase and program cycle endurance of 100,000 cycles.
PRELIMINARY (June, 2000, Version 0.2)
25
AMIC Technology, Inc.
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