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74VHCT373ATTR-2001 Ver la hoja de datos (PDF) - STMicroelectronics

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74VHCT373ATTR(2001) OCTAL D-TYPE LATCH WITH 3 STATE OUTPUTS NON INVERTING ST-Microelectronics
STMicroelectronics ST-Microelectronics
74VHCT373ATTR Datasheet PDF : 10 Pages
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74VHCT373A
OCTAL D-TYPE LATCH
WITH 3 STATE OUTPUTS NON INVERTING
s HIGH SPEED: tPD = 6.4 ns (TYP.) at VCC = 5V
s LOW POWER DISSIPATION:
ICC = 4 µA (MAX.) at TA=25°C
s COMPATIBLE WITH TTL OUTPUTS:
VIH = 2V (MIN.), VIL = 0.8V (MAX)
s POWER DOWN PROTECTION ON INPUTS
& OUTPUTS
s SYMMETRICAL OUTPUT IMPEDANCE:
|IOH| = IOL = 8 mA (MIN)
s BALANCED PROPAGATION DELAYS:
tPLH tPHL
s OPERATING VOLTAGE RANGE:
VCC(OPR) = 4.5V to 5.5V
s PIN AND FUNCTION COMPATIBLE WITH
74 SERIES 373
s IMPROVED LATCH-UP IMMUNITY
s LOW NOISE: VOLP = 0.9V (MAX.)
DESCRIPTION
The 74VHCT373A is an advanced high-speed
CMOS OCTAL D-TYPE LATCH with 3 STATE
OUTPUTS NON INVERTING fabricated with
sub-micron silicon gate and double-layer metal
wiring C2MOS technology.
These 8 bit D-Type latch are controlled by a latch
enable input (LE) and an output enable input (OE).
While the LE inputs is held at a high level, the Q
outputs will follow the data input precisely . When
the LE is taken low, the Q outputs will be latched
PIN CONNECTION AND IEC LOGIC SYMBOLS
SOP
TSSOP
ORDER CODES
PACKAGE
TUBE
T&R
SOP
TSSOP
74VHCT373AM 74VHCT373AMTR
74VHCT373ATTR
precisely at the logic level of D input data. While
the (OE) input is low, the 8 outputs will be in a
normal logic state (high or low logic level) and
while high level the outputs will be in a high
impedance state.
Power down protection is provided on all inputs
and outputs and 0 to 7V can be accepted on
inputs with no regard to the supply voltage. This
device can be used to interface 5V to 3V since all
inputs are equipped with TTL threshold.
All inputs and outputs are equipped with
protection circuits against static discharge, giving
them 2KV ESD immunity and transient excess
voltage.
June 2001
1/10
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