LC7537 View Datasheet(PDF) - SANYO -> Panasonic
Part Name
Description
Manufacturer
LC7537 Datasheet PDF : 11 Pages
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Continued from preceding page.
Pin No. Symbol
LC7537N, 7537AN, 7537NE
Description of Functions
8(2)
L-VSS
35(35)
R-VSS
Main volume control block fader control common terminals. The impedance of pattern
connected to these pins should be as low as possible. Since L–VSS (R–VSS) and VSS
have not been connected inside the LSI, they should be connected together on the outside
in conformance with their individual specifications. Particular attenuation should be paid to
the capacitance assigned to the capacitors put between L–VSS (R–VSS) and VSS, which
will emerge as a residual resistive component when control is turned down for maximum
attenuation.
Intra-IC latch resetting terminal
Remarks
42(42)
INIT
22(20)
CE
Control-setting data at the internal latch will be indeterminate when power has just been
switched on, so that by engaging the “L” level of this pin at power-on, the fader control
may be set at its –∞ position and muting behaviour is engaged (Note: VDD to VEE Level).
Chip enable terminal. When this pin is made “H” to “L”, data is written in the internal latch,
activating the various analog switches. When the “H” level is then restored, transfer of the
data will be enabled.
20(16)
DI
21(17)
CLK
1(43)
VDD
23(21)
VCC
19(15)
VSS
24(22)
VEE
2(3, 7)
41(18, 30, NC
34, 41, 44)
(19)
VDD(NC)
Input terminals for serial data and clock that serve control purposes.
These pins are connected to the relevant power supplies. Exercise caution against VCC
rising earlier than VDD.
No connect pins. Absolutely nothing should be connected here.
VDD subterminal. Connected to VDD or left open.
LC7537AN and
LC7537NE only
No. 2169-4/11
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