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SN74LS113AD View Datasheet(PDF) - Motorola => Freescale

Part Name
Description
Manufacturer
SN74LS113AD
Motorola
Motorola => Freescale Motorola
SN74LS113AD Datasheet PDF : 4 Pages
1 2 3 4
DUAL JK NEGATIVE
EDGE-TRIGGERED FLIP-FLOP
The SN54 / 74LS113A offers individual J, K, set, and clock inputs. These
monolithic dual flip-flops are designed so that when the clock goes HIGH, the
inputs are enabled and data will be accepted. The logic level of the J and K
inputs may be allowed to change when the clock pulse is HIGH and the
bistable will perform according to the truth table as long as minimum setup
times are observed. Input data is transferred to the outputs on the
negative-going edge of the clock pulse.
SN54/74LS113A
DUAL JK NEGATIVE
EDGE-TRIGGERED FLIP-FLOP
LOW POWER SCHOTTKY
LOGIC DIAGRAM (Each Flip-Flop)
Q
5(9)
J
3(11)
1(13)
CLOCK (CP)
Q
6(8)
SET (SD)
4(10)
K
2(12)
MODE SELECT — TRUTH TABLE
OPERATING MODE
INPUTS
SD J
K
OUTPUTS
QQ
Set
Toggle
Load “0” (Reset)
Load “1” (Set)
Hold
L
X
X
H
L
H
h
h
q
q
H
l
h
L
H
H
h
l
H
L
H
l
l
q
q
H, h = HIGH Voltage Level
L, I = LOW Voltage Level
X = Don’t Care
l, h (q) = Lower case letters indicate the state of the referenced input (or output)
l, h (q) = one set-up time prior to the HIGH to LOW clock transition.
14
1
J SUFFIX
CERAMIC
CASE 632-08
14
1
N SUFFIX
PLASTIC
CASE 646-06
14
1
D SUFFIX
SOIC
CASE 751A-02
ORDERING INFORMATION
SN54LSXXXJ Ceramic
SN74LSXXXN Plastic
SN74LSXXXD SOIC
LOGIC SYMBOL
4
10
3
SD
J
Q
11
SD
5
J
Q
9
1
CP
13
CP
2
K
12
Q
6
K
Q
8
VCC = PIN 14
GND = PIN 7
FAST AND LS TTL DATA
5-189
 

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