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MC74F112D 查看數據表(PDF) - Motorola => Freescale

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MC74F112D DUAL JK NEGATIVE EDGE-TRIGGERED FLIP-FLOP Motorola
Motorola => Freescale Motorola
MC74F112D Datasheet PDF : 3 Pages
1 2 3
DUAL JK NEGATIVE
EDGE-TRIGGERED FLIP-FLOP
The MC74F112 contains two independent, high-speed JK flip-flops with Di-
rect Set and Clear inputs. Synchronous state changes are initiated by the fal-
ling edge of the clock. Triggering occurs at a voltage level of the clock and is
not directly related to the transition time. The J and K inputs can change when
the clock is in either state without affecting the flip-flop, provided that they are
in the desired state during the recommended setup and hold times relative to
the falling edge of the clock. A LOW signal on SD or CD prevents clocking and
forces Q or Q HIGH, respectively. Simultaneous LOW signals on SD and CD
force both Q and Q HIGH.
CONNECTION DIAGRAM
VCC CD1 CD2 CP2 K2 J2 SD2 Q2
16 15 14 13 12 11 10 9
K CD Q
CP
J SD Q
J SD Q
CP
K CD Q
12345678
CP1 K1 J1 SD1 Q1 Q1 Q2 GND
FUNCTION TABLE (Each Half)
Inputs
Output
@ tn
JK
@ tn + 1
Q
LL
Qn
LH
L
HL
H
HH
Qn
Asynchronous Inputs:
LOW Input to SD sets Q to HIGH level
LOW Input to CD sets Q to LOW level
Clear and Set are independent of clock
Simultaneous LOW on CD and SD makes both Q and Q HIGH
H = HIGH Voltage Level
L = LOW Voltage Level
tn = Bit time before clock pulse
tn + 1 = Bit time after clock pulse
MC74F112
DUAL JK NEGATIVE
EDGE-TRIGGERED FLIP-FLOP
FASTSCHOTTKY TTL
16
1
16
1
J SUFFIX
CERAMIC
CASE 620-09
N SUFFIX
PLASTIC
CASE 648-08
16
1
D SUFFIX
SOIC
CASE 751B-03
ORDERING INFORMATION
MC74FXXXJ
MC74FXXXN
MC74FXXXD
Ceramic
Plastic
SOIC
LOGIC SYMBOL
4
10
3
J SD Q
5 11
J SD Q
9
1 CP
13 CP
2
K Q 6 12
K CD Q
7
15
14
VCC = PIN 16
GND = PIN 8
FAST AND LS TTL DATA
4-45
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