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74ACT74TTR 데이터 시트보기 (PDF) - STMicroelectronics

부품명74ACT74TTR ST-Microelectronics
STMicroelectronics ST-Microelectronics
상세내역DUAL D-TYPE FLIP FLOP WITH PRESET AND CLEAR
74ACT74TTR Datasheet PDF : 11 Pages
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74ACT74
DC SPECIFICATIONS
Test Condition
Value
Symbol
Parameter
VCC
(V)
TA = 25°C
Min. Typ. Max.
VIH High Level Input
4.5
VO = 0.1 V or
2.0 1.5
Voltage
5.5
VCC-0.1V
2.0 1.5
VIL Low Level Input
4.5
Voltage
5.5
VOH High Level Output 4.5
Voltage
5.5
VO = 0.1 V or
VCC-0.1V
IO=-50 µA
IO=-50 µA
1.5 0.8
1.5 0.8
4.4 4.49
5.4 5.49
4.5
5.5
VOL Low Level Output 4.5
Voltage
5.5
IO=-24 mA
IO=-24 mA
IO=50 µA
IO=50 µA
3.86
4.86
0.001 0.1
0.001 0.1
4.5
IO=24 mA
5.5
IO=24 mA
II
Input Leakage Cur-
rent
5.5
VI = VCC or GND
0.36
0.36
± 0.1
ICCT Max ICC/Input
5.5 VI = VCC - 2.1V
0.6
ICC
Quiescent Supply
Current
5.5 VI = VCC or GND
4
IOLD
IOHD
Dynamic Output
Current (note 1, 2)
5.5 VOLD = 1.65 V max
VOHD = 3.85 V min
1) Maximum test duration 2ms, one output loaded at time
2) Incident wave switching is guaranteed on transmission lines with impedances as low as 50
-40 to 85°C -55 to 125°C
Min. Max. Min. Max.
2.0
2.0
2.0
2.0
0.8
0.8
0.8
0.8
4.4
4.4
5.4
5.4
3.76
3.7
4.76
4.7
0.1
0.1
0.1
0.1
0.44
0.5
0.44
0.5
±1
±1
1.5
1.6
40
40
75
50
-75
-50
Unit
V
V
V
µA
mA
µA
mA
mA
AC ELECTRICAL CHARACTERISTICS (CL = 50 pF, RL = 500 , Input tr = tf = 3ns)
Test Condition
Value
Symbol
Parameter
VCC
(V)
tPLH tPHL Propagation Delay
Time CK to Q or Q
5.0(*)
tPLH tPHL Propagation Delay
Time PR or CLR to 5.0(*)
Q or Q
tW Pulse Width HIGH
or LOW, CK or PR 5.0(*)
or CLR
ts
Setup Time D to CK
HIGH or LOW
5.0(*)
th
Hold Time D to CK
HIGH or LOW
5.0(*)
tREM
Removal Tim|
PR or CLR to CK
5.0(*)
fMAX Maximum Clock
Frequency
5.0(*)
TA = 25°C
-40 to 85°C -55 to 125°C Unit
Min. Typ. Max. Min. Max. Min. Max.
5.0 10.0
11.0
11.0 ns
5.0 10.0
11.0
11.0 ns
1.5 5.0
6.0
6.0 ns
0.5 3.0
3.5
3.5 ns
-0.5 1.0
1.0
1.0 ns
-0.7 1.0
1.0
1.0 ns
100 250
85
85
MHz
(*) Voltage range is 5.0V ± 0.5V
4/12
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DESCRIPTION
The 74ACT74 is an advanced high-speed CMOS DUAL D-TYPE FLIP FLOP WITH PRESET AND
CLEAR fabricated with sub-micron silicon gate and double-layer metal wiring C2MOS tecnology.
A signal on the D INPUT is transferred to the Q and QOUTPUTS during the positive going
transition of the clock pulse.
CLEAR and PRESET are independent of the clock and accomplished by a low setting on the
appropriate input. The device is designed to interface directly High Speed CMOS systems with TTL, NMOS and CMOS output voltage levels. All inputs and outputs are equipped with protection circuits against static discharge, giving them 2KV ESD immunity and transient excess voltage.

■ HIGH SPEED:  fMAX= 250MHz (TYP.) at VCC= 5V
■ LOW POWER DISSIPATION: ICC= 4µA(MAX.) at TA=25°C
■ COMPATIBLE WITH TTL OUTPUTS
    VIH= 2V (MIN.), VIL = 0.8V (MAX.)
■ 50ΩTRANSMISSION LINE DRIVING CAPABILITY
■ SYMMETRICAL OUTPUT IMPEDANCE: |IOH| = IOL= 24mA (MIN)
■ BALANCED PROPAGATION DELAYS: tPLH ≅tPHL
■ OPERATING VOLTAGE RANGE: VCC(OPR) = 4.5V to 5.5V
■ PIN AND FUNCTION COMPATIBLE WITH 74 SERIES 74
■ IMPROVED LATCH-UP IMMUNITY

 

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