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74ACT74TTR 데이터 시트보기 (PDF) - STMicroelectronics

부품명74ACT74TTR ST-Microelectronics
STMicroelectronics ST-Microelectronics
상세내역DUAL D-TYPE FLIP FLOP WITH PRESET AND CLEAR
74ACT74TTR Datasheet PDF : 11 Pages
1 2 3 4 5 6 7 8 9 10 Next Last
74ACT74
INPUT AND OUTPUT EQUIVALENT CIRCUIT
TRUTH TABLE
INPUTS
CLR
PR
D
CK
L
H
X
X
H
L
X
X
L
L
X
X
H
H
L
H
H
H
H
H
X
X : Don’t Care
LOGIC DIAGRAM
PIN DESCRIPTION
PIN No
1, 13
2, 12
3, 11
4, 10
5, 9
6, 8
7
14
SYMBOL NAME AND FUNCTION
1CLR, 2CLR
Asyncronous Reset -
Direct Input
1D, 2D Data Inputs
1CK, 2CK Clock Input
(LOW to HIGH, Edge
Triggered)
1PR, 2PR Asyncronous Set - Direct
Input
1Q, 2Q True Flip-Flop Outputs
1Q, 2Q Complement Flip-Flop
Outputs
GND Ground (0V)
VCC
Positive Supply Voltage
OUTPUTS
Q
Q
L
L
H
L
H
H
L
H
H
L
Qn
Qn
FUNCTION
CLEAR
PRESET
NO CHANGE
This logic diagram has not be used to estimate propagation delays
2/12
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DESCRIPTION
The 74ACT74 is an advanced high-speed CMOS DUAL D-TYPE FLIP FLOP WITH PRESET AND
CLEAR fabricated with sub-micron silicon gate and double-layer metal wiring C2MOS tecnology.
A signal on the D INPUT is transferred to the Q and QOUTPUTS during the positive going
transition of the clock pulse.
CLEAR and PRESET are independent of the clock and accomplished by a low setting on the
appropriate input. The device is designed to interface directly High Speed CMOS systems with TTL, NMOS and CMOS output voltage levels. All inputs and outputs are equipped with protection circuits against static discharge, giving them 2KV ESD immunity and transient excess voltage.

■ HIGH SPEED:  fMAX= 250MHz (TYP.) at VCC= 5V
■ LOW POWER DISSIPATION: ICC= 4µA(MAX.) at TA=25°C
■ COMPATIBLE WITH TTL OUTPUTS
    VIH= 2V (MIN.), VIL = 0.8V (MAX.)
■ 50ΩTRANSMISSION LINE DRIVING CAPABILITY
■ SYMMETRICAL OUTPUT IMPEDANCE: |IOH| = IOL= 24mA (MIN)
■ BALANCED PROPAGATION DELAYS: tPLH ≅tPHL
■ OPERATING VOLTAGE RANGE: VCC(OPR) = 4.5V to 5.5V
■ PIN AND FUNCTION COMPATIBLE WITH 74 SERIES 74
■ IMPROVED LATCH-UP IMMUNITY

 

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