datasheetq language:

74ACT74TTR 데이터 시트보기 (PDF) - STMicroelectronics

부품명74ACT74TTR ST-Microelectronics
STMicroelectronics ST-Microelectronics
상세내역DUAL D-TYPE FLIP FLOP WITH PRESET AND CLEAR
74ACT74TTR Datasheet PDF : 11 Pages
1 2 3 4 5 6 7 8 9 10 Next Last
74ACT74
DUAL D-TYPE FLIP FLOP WITH PRESET AND CLEAR
s HIGH SPEED:
fMAX = 250MHz (TYP.) at VCC = 5V
s LOW POWER DISSIPATION:
ICC = 4µA(MAX.) at TA=25°C
s COMPATIBLE WITH TTL OUTPUTS
VIH = 2V (MIN.), VIL = 0.8V (MAX.)
s 50TRANSMISSION LINE DRIVING
CAPABILITY
s SYMMETRICAL OUTPUT IMPEDANCE:
|IOH| = IOL = 24mA (MIN)
s BALANCED PROPAGATION DELAYS:
tPLH tPHL
s OPERATING VOLTAGE RANGE:
VCC (OPR) = 4.5V to 5.5V
s PIN AND FUNCTION COMPATIBLE WITH
74 SERIES 74
s IMPROVED LATCH-UP IMMUNITY
DESCRIPTION
The 74ACT74 is an advanced high-speed CMOS
DUAL D-TYPE FLIP FLOP WITH PRESET AND
CLEAR fabricated with sub-micron silicon gate
and double-layer metal wiring C2MOS tecnology.
A signal on the D INPUT is transferred to the Q
and Q OUTPUTS during the positive going
transition of the clock pulse.
DIP
SOP
TSSOP
ORDER CODES
PACKAGE
DIP
SOP
TSSOP
TUBE
74ACT74B
74ACT74M
T&R
74ACT74MTR
74ACT74TTR
CLEAR and PRESET are independent of the
clock and accomplished by a low setting on the
appropriate input.
The device is designed to interface directly High
Speed CMOS systems with TTL, NMOS and
CMOS output voltage levels.
All inputs and outputs are equipped with
protection circuits against static discharge, giving
them 2KV ESD immunity and transient excess
voltage.
PIN CONNECTION AND IEC LOGIC SYMBOLS
April 2001
1/12
Direct download click here

DESCRIPTION
The 74ACT74 is an advanced high-speed CMOS DUAL D-TYPE FLIP FLOP WITH PRESET AND
CLEAR fabricated with sub-micron silicon gate and double-layer metal wiring C2MOS tecnology.
A signal on the D INPUT is transferred to the Q and QOUTPUTS during the positive going
transition of the clock pulse.
CLEAR and PRESET are independent of the clock and accomplished by a low setting on the
appropriate input. The device is designed to interface directly High Speed CMOS systems with TTL, NMOS and CMOS output voltage levels. All inputs and outputs are equipped with protection circuits against static discharge, giving them 2KV ESD immunity and transient excess voltage.

■ HIGH SPEED:  fMAX= 250MHz (TYP.) at VCC= 5V
■ LOW POWER DISSIPATION: ICC= 4µA(MAX.) at TA=25°C
■ COMPATIBLE WITH TTL OUTPUTS
    VIH= 2V (MIN.), VIL = 0.8V (MAX.)
■ 50ΩTRANSMISSION LINE DRIVING CAPABILITY
■ SYMMETRICAL OUTPUT IMPEDANCE: |IOH| = IOL= 24mA (MIN)
■ BALANCED PROPAGATION DELAYS: tPLH ≅tPHL
■ OPERATING VOLTAGE RANGE: VCC(OPR) = 4.5V to 5.5V
■ PIN AND FUNCTION COMPATIBLE WITH 74 SERIES 74
■ IMPROVED LATCH-UP IMMUNITY

 

Share Link : ST-Microelectronics

Language : English   日本語   русский   简体中文   español
@ 2015 - 2017  [ Home  ] [ Privacy Policy ] [ Request Datasheet  ] [ Contact Us ]