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74LV4052 查看數據表(PDF) - Philips Electronics

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74LV4052 Dual 4-channel analog multiplexer/demultiplexer Philips
Philips Electronics Philips
74LV4052 Datasheet PDF : 16 Pages
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Philips Semiconductors
Dual 4-channel analog multiplexer/demultiplexer
Product specification
74LV4052
FEATURES
Optimized for low voltage applications: 1.0 to 6.0 V
Accepts TTL input levels between VCC = 2.7 V and VCC = 3.6 V
Low typ “ON” resistance:
60 W at Vcc – VEE = 4.5 V
90 W at Vcc – VEE = 3.0 V
145 W at Vcc – VEE = 2.0 V
Logic level translation: to enable 3 V logic to communicate with ± 3
V analog signals
Typical “break before make” built in
Analog/Digital multiplexing and demultiplexing
Signal gating
Output capability: non-standard
ICC category: MSI
DESCRIPTION
The 74LV4052 is a low-voltage CMOS device and is pin and
function compatible with the 74HC/HCT4052.
The 74LV4052 is a dual 4-channel analog multiplexer/demultiplexer
with a common select logic. Each multiplexer has four independent
inputs/outputs (nY0 to nY3) and a common input/output (nZ). The
common channel select logics include two digital select inputs (S0
and S1) and an active LOW enable input (E).
With E LOW, one of the four switches is selected (low impedance
ON-state) by S0 and S1. With E HIGH, all switches are in the high
impedance OFF-state, independent of S0 and S1. VCC and GND are
the supply voltage pins for the digital control inputs (S0, S1 and E).
The VCC to GND ranges are 1.0 to 6.0 V. The analog inputs/outputs
(nY0, to nY3, and nZ) can swing between VCC as a positive limit and
VEE as a negative limit. VCC - VEE may not exceed 6.0 V. For
operation as a digital multiplexer/demultiplexer, VEE is connected to
GND (typically ground).
QUICK REFERENCE DATA
GND = 0 V; Tamb = 25°C; tr =tf 2.5 ns
SYMBOL
PARAMETER
CONDITIONS
tPZH/tPZL
tPHZ/tPLZ
CI
CPD
CS
Turn “ON” time
E or VOS Sn
Turn “OFF” time
E or VOS Sn
Input capacitance
Power dissipation capacitance per switch
Maximum switch capacitance
independent (Y) common (Z)
CL = 15 pF
RL = 1KW
VCC = 3.3 V
See Notes 1 and 2
NOTES:
1.
PCDPD=isCPuDse×dVtoCCd2et×erfmi )inȍe
the dynamic
((CL + CS) ×
power dissipation
VCC2 × fo) where:
(PD
in
µW)
fi = input frequency in MHz; CL = output load capacity in pF;
fo = output frequency in MHz; CS = maximum switch capacitance in pF;
ȍVC(C(C=L
supply voltage
+CS) × VCC2 ×
in V;
fo) =
sum
of
the
outputs.
2. The condition is VI = GND to VCC.
TYPICAL
30
22
3.5
57
5
12
UNIT
ns
pF
ORDERING INFORMATION
PACKAGES
16-Pin Plastic DIL
16-Pin Plastic SO
16-Pin Plastic SSOP Type II
16-Pin Plastic TSSOP Type I
TEMPERATURE RANGE
–40°C to +125°C
–40°C to +125°C
–40°C to +125°C
–40°C to +125°C
OUTSIDE NORTH AMERICA
74LV4052 N
74LV4052 D
74LV4052 DB
74LV4052 PW
NORTH AMERICA
74LV4052 N
74LV4052 D
74LV4052 DB
74LV4052PW DH
Code
SOT38-4
SOT109-1
SOT338-1
SOT403-1
PIN CONFIGURATION
2Y0 1
2Y2 2
2Z 3
2Y3 4
2Y1 5
E6
VEE 7
GND 8
16 VCC
15 1Y2
14 1Y1
13 1Z
12 1Y0
11 1Y3
10 S0
9 S1
SV01697
PIN DESCRIPTION
PIN NUMBER SYMBOL
1, 5, 2, 4
6
2Y0, 2Y3
E
7
VEE
8
GND
10, 9
12, 14, 15, 11
13, 3
S0, S1
1Y0 to 1Y3
1Z, 2Z
16
VCC
FUNCTION
Independent inputs/outputs
Enable input (active LOW)
Negative supply voltage
Ground (0 V)
Select inputs
Independent inputs/outputs
Common inputs/outputs
Positive supply voltage
1998 Jun 23
2
853-1999 19618
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