XR16C850 View Datasheet(PDF) - Exar Corporation
Part Name
Description
Manufacturer
XR16C850 Datasheet PDF : 55 Pages
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XR16C850
Transmit and Receive Holding Register
The serial transmitter section consists of an 8-bit
Transmit Hold Register (THR) and Transmit Shift Reg-
ister (TSR). The status of the THR is provided in the Line
Status Register (LSR). Writing to the THR transfers the
contents of the data bus (D7-D0) to the THR, providing
that the THR or TSR is empty. The THR empty flag in the
LSR register will be set to a logic 1 when the transmitter
is empty or when data is transferred to the TSR. Note
that a write operation can be performed when the
transmit holding register empty flag is set (logic 0 =
FIFO full, logic 1= at least one FIFO location available).
The serial receive section also contains an 8-bit Receive
Holding Register, RHR. Receive data is removed from
the 850 and receive FIFO by reading the RHR register.
The receive section provides a mechanism to prevent
false starts. On the falling edge of a start or false start
bit, an internal receiver counter starts counting clocks
at 16x clock rate. After 7 1/2 clocks the start bit time
should be shifted to the center of the start bit. At this
time the start bit is sampled and if it is still a logic 0 it
is validated. Evaluating the start bit in this manner
prevents the receiver from assembling a false character.
Receiver status codes will be posted in the LSR.
Device Identification
The XR16C850 provides Device identification and De-
vice Revision code to distinguish the part from others. It
is suggested to read the identification and revision
information from the part only during the power on
initialization routine to avoid disturbing the baud rate
generator.
To read the identification number from the device, it is
required to set the baud rate generator divisor latch to “1”
(LCR bit-7 = logic 1) and set the content of the baud rate
generator DLL and DLM registers to “00” hex. Then read
the content of DLM for “10” hex for XR16C850 and the
content of DLL for the revision of the part.
Interrupt Enable Register (IER)
The Interrupt Enable Register (IER) masks the inter-
rupts from receiver ready, transmitter empty, line status
and modem status registers. These interrupts would
normally be seen on the 850 INT output pin.
IER Vs Receive FIFO Interrupt Mode Operation
When the receive FIFO (FCR BIT-0 = a logic 1) and
receive interrupts (IER BIT-0 = logic 1) are enabled, the
receive interrupts and register status will reflect the
following:
A) The receive data available interrupts are issued to the
external CPU when the FIFO has reached the pro-
grammed trigger level. It will be cleared when the FIFO
drops below the programmed trigger level.
B) FIFO status will also be reflected in the user acces-
sible ISR register when the FIFO trigger level is reached.
Both the ISR register status bit and the interrupt will be
cleared when the FIFO drops below the trigger level.
C) The data ready bit (LSR BIT-0) is set as soon as a
character is transferred from the shift register to the
receive FIFO. It is reset when the FIFO is empty.
IER Vs Receive/Transmit FIFO Polled Mode Opera-
tion
When FCR BIT-0 equals a logic 1; resetting IER bits 0-
3 enables the 850 in the FIFO polled mode of operation.
Since the receiver and transmitter have separate bits in
the LSR either or both can be used in the polled mode
by selecting respective transmit or receive control bit(s).
A) LSR BIT-0 will be a logic 1 as long as there is one byte
in the receive FIFO.
B) LSR BIT 1-4 will indicate if an overrun error occurred
in the receiver.
C) LSR BIT-5 will indicate when the transmit FIFO is
empty.
D) LSR BIT-6 will indicate when both the transmit FIFO
and transmit shift register are empty.
E) LSR BIT-7 will indicate any data errors within the
receive FIFO. This bit will clear when the error byte is
unloaded.
IER BIT-0:
Logic 0 = Disable the receiver ready interrupt. (normal
default condition)
Rev. 1.20
26
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