XR16C850 View Datasheet(PDF) - Exar Corporation

Part Name

Description

Manufacturer

XR16C850

UART with 128-byte FIFO’s FIFO Counters and Half-duplex Control

Exar Corporation 

XR16C850

DMA Operation

The 850 FIFO trigger level provides additional flexibility

to the user for block transfer operation. LSR bits 5-6

provide an indication when the transmitter is empty or

has an empty location(s). The user can optionally

operate the transmit and receive FIFOs in the DMA

mode (FCR bit-3). When the transmit and receive FIFOs

are enabled and the DMA mode is deactivated (DMA

Mode “0”), the 850 activates the interrupt output pin for

each data transmit or receive operation. When DMA

mode is activated (DMA Mode “1”), the user takes the

advantage of block mode operation by loading or unload-

ing the FIFO in a block sequence determined by the

preset trigger level. In this mode, the 850 sets the

interrupt output pin when characters in the transmit

FIFOs are below the transmit trigger level, or the

characters in the receive FIFOs are above the receive

trigger level. Transmit or receive DMA operation is

selected by EMSR register bit 2.

Sleep Mode

The 850 is designed to operate with low power con-

sumption. A sleep mode is included to further reduce

power consumption when the chip is not being used.

The operating parameters are maintained while in sleep

mode. With EFR bit-4 and IER bit-4 enabled (set to a

logic 1), the 850 enters the sleep mode when no

interrupt is pending and no activities on the modem port.

If an external clock is supplied to the 850, you may want

to stop it. The 850 resumes normal operation when a RX

character’s start bit is detected, a change of state on

any of the modem input pins RX, -RI, -CTS, -DSR, -CD,

or transmit data is loaded into the FIFO by the user. It

typically takes 30us for the crystal oscillator to restart

from sleep mode depending on the crystal properties.

This delay must be taken into consideration during

design as Rx character(s) may be lost since it depends

on the operating bit rate. If the sleep mode is enabled

and the 850 is awakened by one of the conditions

described above, it will return to the sleep mode auto-

matically after the last character is transmitted or read

by the user and no interrupt is pending. In any case, the

chip will not enter sleep mode while an interrupt(s) is still

pending and the oscillator would still be running. The

850 will stay in the sleep mode of operation until it is

disabled by setting IER bit-4 to a logic 0.

Sleep mode enable during initialization example:

Write LCR with “BF” hex

Set EFR bit-4 to logic 1

Write LCR with op. value

Set IER bit-4 to logic 1

; access to EFR registers

; enable enhanced function bits

; set LCR with op. parameters

; enable sleep mode.

; It goes to sleep when:

; no pending interrupt,

; no modem port activity then enters

; sleep mode by stopping osc.

For lowest sleep current the following pins should be left at logic

1 state: S1, S2, A4, A9, BUS8/16, CLK8/16, CLKSEL, -DMA, -DACK,

SEL, TC and RX.

Loopback Mode

The internal loopback capability allows onboard diag-

nostics. In this mode, the normal modem interface pins

are disconnected and reconfigured for loopback inter-

nally. MSR bits 4-7 are also disconnected. However,

MCR register bits 0-3 can be used for controlling

loopback diagnostic testing. In this mode, OP1 and

OP2 in the MCR register (bits 0-1) control the modem

-RI and -CD inputs respectively. MCR signals -DTR and

-RTS (bits 0-1) are used to control the modem -CTS and

-DSR inputs respectively. The transmitter output (TX)

and the receiver input (RX) are disconnected from their

associated interface pins, and instead are connected

together internally (See Figure 12). The -CTS, -DSR,

-CD, and -RI are disconnected from their normal

modem control inputs pins, and instead are connected

internally to -DTR, -RTS, -OP1 and -OP2. Loopback test

data is entered into the transmit holding register via the

user data bus interface, D0-D7. The transmit UART

serializes the data and passes the serial data to the

receive UART via the internal loopback connection. The

receive UART converts the serial data back into parallel

data that is then made available at the user data

interface, D0-D7. The user optionally compares the

received data to the initial transmitted data for verifying

error free operation of the UART TX/RX circuits. In this

mode, the receiver, transmitter and modem control

interrupts are fully operational. However, the interrupts

can only be read using lower four bits of the Modem

Control Register (MCR bits 0-3) instead of the four

Modem Status Register bits 4-7. The interrupts are still

controlled by the IER.

Rev. 1.20

22

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