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X1227G View Datasheet(PDF) - Intersil

Part NameDescriptionManufacturer
X1227G 2-Wire™ RTC Real TimeClock/Calendar/CPU Supervisor with EEPROM Intersil
Intersil Intersil
X1227G Datasheet PDF : 28 Pages
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X1227
DESCRIPTION (continued)
The Real-Time Clock keeps track of time with
separate registers for Hours, Minutes, Seconds. The
Calendar has separate registers for Date, Month, Year
and Day-of-week. The calendar is correct through
2099, with automatic leap year correction.
The powerful Dual Alarms can be set to any
Clock/Calendar value for a match. For instance, every
minute, every Tuesday, or 5:23 AM on March 21. The
alarms can be polled in the Status Register. There is a
repeat mode for the alarms allowing a periodic interrupt.
The X1227 device integrates CPU Supervisor func-
tions and a Battery Switch. There is a Power-On Reset
(RESET output) with typically 250 ms delay from
power-on. It will also assert RESET when Vcc goes
below the specified threshold. The Vtrip threshold is
user repro-grammable. There is a WatchDog Timer
(WDT) with 3 selectable time-out periods (0.25s,
0.75s, 1.75s) and a disabled setting. The watchdog
activates the RESET pin when it expires.
The device offers a backup power input pin. This
VBACK pin allows the device to be backed up by
battery or SuperCap. The entire X1227 device is fully
operational from 2.7 to 5.5 volts and the
clock/calendar portion of the X1227 device remains
fully operational down to 1.8 volts (Standby Mode).
The X1227 device provides 4K bits of EEPROM with 8
modes of BlockLock™ control. The BlockLock allows a
safe, secure memory for critical user and configuration
data, while allowing a large user storage area.
PIN DESCRIPTIONS
X1
X2
RESET
VSS
X1227
8 LD SOIC
1
8
2
7
3
6
4
5
VCC
VBACK
SCL
SDA
VBACK
VCC
X1
X2
X1227
8 LD TSSOP
1
8
2
7
3
6
4
5
SCL
SDA
VSS
RESET
NC = No internal connection
Serial Clock (SCL)
The SCL input is used to clock all data into and out of
the device. The input buffer on this pin is always active
(not gated).
Serial Data (SDA)
SDA is a bidirectional pin used to transfer data into and
out of the device. It has an open drain output and may
be wire ORed with other open drain or open collector
outputs. The input buffer is always active (not gated).
An open drain output requires the use of a pull-up
resistor. The output circuitry controls the fall time of
the output signal with the use of a slope controlled
pull-down. The circuit is designed for 400kHz 2-wire
interface speeds.
VBACK
This input provides a backup supply voltage to the
device. VBACK supplies power to the device in the
event the VCC supply fails. This pin can be connected
to a battery, a Supercap or tied to ground if not used.
RESET Output – RESET
This is a reset signal output. This signal notifies a host
processor that the watchdog time period has expired or
that the voltage has dropped below a fixed VTRIP thresh-
old. It is an open drain active LOW output. Recom-
mended value for the pullup resistor is 5kΩ. If unused, tie
to ground.
X1, X2
The X1 and X2 pins are the input and output,
respectively, of an inverting amplifier. An external
32.768kHz quartz crystal is used with the X1227 to
supply a timebase for the real time clock. The
recommended crystal is a Citizen CFS206-32.768KDZF.
Internal compensation circuitry is included to form a
complete oscillator circuit. Care should be taken in the
placement of the crystal and the layout of the circuit.
Plenty of ground plane around the device and short
traces to X1 and X2 are highly recommended. See
Application section for more recommendations.
Figure 2. Recommended Crystal connection
X1
X2
9
FN8099.2
May 8, 2006
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