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X1226V8Z View Datasheet(PDF) - Intersil

Part NameDescriptionManufacturer
X1226V8Z 4K (512 x 8), 2-Wire™ RTC Intersil
Intersil Intersil
X1226V8Z Datasheet PDF : 25 Pages
1 2 3 4 5 6 7 8 9 10 Next Last
X1226
PIN ASSIGNMENTS
Pin Number
SOIC TSSOP Symbol
1
3
X1
2
4
X2
3
5
PHZ/IRQ
4
6
VSS
5
7
SDA
6
8
SCL
7
1
VBACK
8
2
VCC
Brief Description
X1. The X1pin is the input of an inverting amplifier. An external 32.768kHz quartz
crystal is used with the X1226 to supply a timebase for the real time clock. The
recommended crystal is a Citizen CFS206-32.768KDZF. Internal compensation circuitry is
included to form a complete oscillator circuit. Care should be taken in the placement of the
crystal and the layout of the circuit. Plenty of ground plane around the device and short
traces to X1 are highly recommended. See Application section for more recommendations.
X2. The X2 pin is the output of an inverting amplifier. An external 32.768kHz quartz
crystal is used with the X1226 to supply a timebase for the real time clock. The
recommended crystal is a Citizen CFS206-32.768KDZF. Internal compensation circuitry is
included to form a complete oscillator circuit. Care should be taken in the placement of the
crystal and the layout of the circuit. Plenty of ground plane around the device and short
traces to X2 are highly recommended. See Application section for more recommendations.
Programmable Frequency/Interrupt Output – PHZ/IRQ. This is either an output from
the internal oscillator or an interrupt signal output. It is an open drain output.
When used as frequency output, this signal has a frequency of 32.768kHz, 4096Hz,
1Hz or inactive.
When used as interrupt output, this signal notifies a host processor that an alarm has
occurred and an action is required. It is an active LOW output.
The control bits for this function are FO1 and FO0 and are found in address 0011h of
the Clock Control Memory map. See “Programmable Frequency Output Bits—FO1,
FO0” on page 9.
VSS.
Serial Data (SDA). SDA is a bidirectional pin used to transfer data into and out of the
device. It has an open drain output and may be wire ORed with other open drain or
open collector outputs. The input buffer is always active (not gated).
An open drain output requires the use of a pull-up resistor. The output circuitry controls
the fall time of the output signal with the use of a slope controlled pull-down. The circuit
is designed for 400kHz 2-wire interface speed.
Serial Clock (SCL). The SCL input is used to clock all data into and out of the device.
The input buffer on this pin is always active (not gated).
VBACK. This input provides a backup supply voltage to the device. VBACK supplies
power to the device in the event the VCC supply fails. This pin can be connected to a
battery, a Supercap or tied to ground if not used.
VCC.
3
FN8098.3
May 8, 2006
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