WM8144-12
Theory of Operation (Contd)
Example of Gain and Offset Operation
Input Video polarity
negative
Input sampling
CDS
Input voltage amplitude (VVS - VRS) 1.6V
Programmable gain
x1
Clamping
Yes, VCL = 3.5V
After the input capacitor the input to the WM8144-12 can
be represented as:
Vrs
Vvs
RS
VS
Figure 7
For a black pixel:
VRS = VCL
VVS = VCL
Assuming that the offset DAC is set to 00dec:
VADC
=
1*
(Vcl
-
Vcl)
+
(1−
2
*
0)
*
0
255
VMID
*
VMID
2
+
VMID
VADC = 0 + 0 + VMID
VADC = VMID
An input voltage of VMID corresponds to a code of
2048(dec) from the ADC.
To maximise the dynamic range of the ADC input it is
necessary to program the offset DAC code to move the
ADC code corresponding to the black level towards code
4096(dec).
Hence set the offset DAC to 164(dec) with the sign bit
not set.
164 VMID
VADC = 1*(VCL - VCL) + (1 - 2*0) *
*
+ VMID
255 2
82
VADC = 0 + 255 * VMID + VMID
337
VADC = 255 * VMID
When the VMID is 2.5v, the ADC input voltage becomes
3.3 volts which will result in an ADC code of 3686(dec).
This is near the ideal full-scale of 4095(dec).
For a white pixel:
VRS = VCL
VVS = VCL - 1.6
For the white pixel, using the same offset DAC value, the
ADC input can be expressed as:
164 VMID
VADC = 1*(VCL - 1.6 - VCL) + (1 - 2*0) *
*
+ VMID
255 2
82
VADC = -1.6 + 255 * VMID + VMID
337
VADC = 255 * VMID - 1.6
When the VMID is 2.5V, the ADC input voltage becomes
1.7 volts which will result in a code of 409(dec). This is
near the ideal full-scale of 000(dec).
Therefore the output codes from the ADC are between
3686(dec) and 409(dec), which implies that the ADC
input has been set up to maximise the dynamic range
available. If a digital representation of the ADC output
with a black level near 000(dec) and a white level near
4095(dec) is required then the INVOP control bit should
now be set to ONE.
Wolfson Microelectronics
12