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W39V040B View Datasheet(PDF) - Winbond

Part NameDescriptionManufacturer
W39V040B 512K × 8 CMOS FLASH MEMORY WITH LPC INTERFACE Winbond
Winbond Winbond
W39V040B Datasheet PDF : 32 Pages
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W39V040B
Erase algorithm has completed, #Data Polling produces “1” on DQ7. An address within any of the
sectors selected for erasure must be provided to read valid status information on DQ7.
Just before the completion of an Embedded Program or Erase operation, DQ7 may change
asynchronously with DQ0-DQ6 while Output Enable (#OE) is set to low. That is, the device may
change from providing status information to valid data on DQ7. Depending on when it samples the DQ7
output, the system may read the status or valid data. Even if the device has completed the program or
erase operation and DQ7 has valid data, the data outputs on DQ0-DQ6 may be still invalid. Valid data
on DQ7-DQ0 will appear on successive read cycles.
RY/#BY: Ready/#Busy
The RY/#BY is a dedicated, open-drain output pin which indicates whether an Embedded Algorithm is in
progress or complete. The RY/#BY status is valid after the rising edge of the final #WE pulse in the command
sequence. Since RY/#BY is an open-drain output, several RY/#BY pins can be tied together in parallel with a
pull-up resistor to VDD.
When the output is low (Busy), the device is actively erasing or programming. When the output is high
(Ready), the device is in the read mode or standby mode.
DQ6: Toggle Bit
Toggle Bit on DQ6 indicates whether an Embedded Program or Erase algorithm is in progress or
complete. Toggle Bit I may be read at any address, and is valid after the rising edge of the final #WE
pulse in the command sequence (before the program or erase operation), and during the sector erase
time-out.
During an Embedded Program or Erase algorithm operation, successive read cycles to any address
cause DQ6 to toggle. The system may use either #OE to control the read cycles. Once the operation
has completed, DQ6 stops toggling.
The system can use DQ6 to determine whether a sector is actively erasing. If the device is actively
erasing (i.e., the Embedded Erase algorithm is in progress), DQ6 toggles. If a program address falls
within a protected sector, DQ6 toggles for about 1 µs after the program command sequence is written,
and then returns to reading array data.
DQ5: Exceeded Timing Limits
DQ5 indicates whether the program or erase time has exceeded a specified internal pulse count limit.
DQ5 produces “1” under these conditions which indicates that the program or erase cycle was not
successfully completed.
The device may output “1” on DQ5 if the system tries to program “1” to a location that was previously
programmed to “0.” Only the erase operation can change “0” back to “1.” Under this condition, the
device stops the operation, and while the timing limit has been exceeded, DQ5 produces “1.”
Under both these conditions, the system must write the reset command to return to the read mode.
Multi-Chip Operation
Multiple devices can be wired on the single LPC bus. There are four ID pins can be used to support up
to 16 devices. But in order not to violate the BIOS ROM memory space defined by Intel, Winbond
W39V040A will only used 3 ID pins to allow up to 8 devices, 4Mbytes for BIOS code and 4Mbytes for
registers memory space.
Publication Release Date: April 14, 2005
-7-
Revision A3
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