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W39V040B View Datasheet(PDF) - Winbond

Part NameDescriptionManufacturer
W39V040B 512K × 8 CMOS FLASH MEMORY WITH LPC INTERFACE Winbond
Winbond Winbond
W39V040B Datasheet PDF : 32 Pages
1 2 3 4 5 6 7 8 9 10 Next Last
W39V040B
10.8 Write Cycle Timing Parameters................................................................................... 19
10.9 Data Polling and Toggle Bit Timing Parameters ......................................................... 19
11. TIMING WAVEFORMS FOR PROGRAMMER INTERFACE MODE ....................................... 20
11.1 Read Cycle Timing Diagram ....................................................................................... 20
11.2 Write Cycle Timing Diagram........................................................................................ 20
11.3 Program Cycle Timing Diagram .................................................................................. 21
11.4 #DATA Polling Timing Diagram................................................................................... 21
11.5 Toggle Bit Timing Diagram.......................................................................................... 22
11.6 Sector Erase Timing Diagram ..................................................................................... 22
12. LPC INTERFACE MODE AC CHARACTERISTICS................................................................. 23
12.1 AC Test Conditions ..................................................................................................... 23
12.2 Read/Write Cycle Timing Parameters......................................................................... 23
12.3 Reset Timing Parameters............................................................................................ 23
13. TIMING WAVEFORMS FOR LPC INTERFACE MODE........................................................... 24
13.1 Read Cycle Timing Diagram ....................................................................................... 24
13.2 Write Cycle Timing Diagram........................................................................................ 24
13.3 Program Cycle Timing Diagram .................................................................................. 25
13.4 #DATA Polling Timing Diagram................................................................................... 26
13.5 Toggle Bit Timing Diagram.......................................................................................... 27
13.6 Sector Erase Timing Diagram ..................................................................................... 28
13.7 FGPI Register/Product ID Readout Timing Diagram .................................................. 29
13.8 Reset Timing Diagram................................................................................................. 29
14. ORDERING INFORMATION..................................................................................................... 30
15. HOW TO READ THE TOP MARKING...................................................................................... 30
16. PACKAGE DIMENSIONS ......................................................................................................... 31
16.1 32L PLCC .................................................................................................................... 31
16.2 32L STSOP ................................................................................................................. 31
17. VERSION HISTORY ................................................................................................................. 32
Publication Release Date: April 14, 2005
-2-
Revision A3
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