W25Q20BW View Datasheet(PDF) - Winbond

Part Name

Description

Manufacturer

W25Q20BW

1.8V 2M-BIT SERIAL FLASH MEMORY WITH DUAL AND QUAD SPI

Winbond 

W25Q20BW

Table of Contents

1. GENERAL DESCRIPTION ............................................................................................................... 5

2. FEATURES....................................................................................................................................... 5

3.

PIN CONFIGURATION SOIC 150-MIL AND VSOP 150-MIL ........................................................ 6

4.

PAD CONFIGURATION WSON 6X5-MM, USON 2X3-MM ............................................................. 6

5. PIN DESCRIPTION SOIC 150-MIL, VSOP, WSON 6X5-MM & USON 2X3-MM............................. 6

5.1 Package Types ..................................................................................................................... 7

5.2 Chip Select (/CS) .................................................................................................................. 7

5.3 Serial Data Input, Output and IOs (DI, DO and IO0, IO1, IO2, IO3)..................................... 7

5.4 Write Protect (/WP) .............................................................................................................. 7

5.5 HOLD (/HOLD) ..................................................................................................................... 7

5.6 Serial Clock (CLK) ................................................................................................................ 8

6. BLOCK DIAGRAM ............................................................................................................................ 9

7. FUNCTIONAL DESCRIPTION ....................................................................................................... 10

7.1 SPI OPERATIONS ............................................................................................................. 10

7.1.1 Standard SPI Instructions ....................................................................................................10

7.1.2 Dual SPI Instructions............................................................................................................10

7.1.3 Quad SPI Instructions ..........................................................................................................10

7.1.4 Hold Function .......................................................................................................................10

7.2 WRITE PROTECTION ....................................................................................................... 11

7.2.1 Write Protect Features .........................................................................................................11

8. CONTROL AND STATUS REGISTERS......................................................................................... 12

8.1 STATUS REGISTER .......................................................................................................... 12

8.1.1 BUSY....................................................................................................................................12

8.1.2 Write Enable Latch (WEL) ...................................................................................................12

8.1.3 Block Protect Bits (BP2, BP1, BP0) .....................................................................................12

8.1.4 Top/Bottom Block Protect (TB).............................................................................................12

8.1.5 Sector/Block Protect (SEC) ..................................................................................................12

8.1.6 Complement Protect (CMP) .................................................................................................13

8.1.7 Status Register Protect (SRP1, SRP0) ................................................................................13

8.1.8 Erase/Program Suspend Status (SUS) ................................................................................13

8.1.9 Security Register Lock Bits (LB3, LB2, LB1, LB0)................................................................13

8.1.10 Quad Enable (QE)..............................................................................................................14

8.1.11 Status Register Memory Protection (CMP = 0) ..................................................................15

8.1.12 Status Register Memory Protection (CMP = 1) ..................................................................16

8.2 INSTRUCTIONS................................................................................................................. 17

8.2.1 Manufacturer and Device Identification................................................................................17

8.2.2 Instruction Set Table 1 (Erase, Program Instructions)(1).......................................................18

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