25Q16DWIG View Datasheet(PDF) - Winbond

Part Name

Description

Manufacturer

25Q16DWIG

1.8V 16M-BIT SERIAL FLASH MEMORY WITH DUAL/QUAD SPI & QPI

Winbond 

W25Q16DW

instance, when CMP=0, a top 4KB sector can be protected while the rest of the array is not; when

CMP=1, the top 4KB sector will become unprotected while the rest of the array become read-only. Please

refer to the Status Register Memory Protection table for details. The default setting is CMP=0.

7.1.7 Status Register Protect (SRP1, SRP0)

The Status Register Protect bits (SRP1 and SRP0) are non-volatile read/write bits in the status register

(S8 and S7). The SRP bits control the method of write protection: software protection, hardware

protection, power supply lock-down or one time programmable (OTP) protection.

SRP1 SRP0 /WP

Status

Register

Description

0

0

X

Software /WP pin has no control. The Status register can be written to

Protection after a Write Enable instruction, WEL=1. [Factory Default]

0

1

0

Hardware

Protected

When /WP pin is low the Status Register locked and can not

be written to.

0

1

1

Hardware When /WP pin is high the Status register is unlocked and can

Unprotected be written to after a Write Enable instruction, WEL=1.

1

0

X

Power Supply Status Register is protected and can not be written to again

Lock-Down until the next power-down, power-up cycle.(1)

1

1

X

One Time Status Register is permanently protected and can not be

Program(2) written to.

Note:

1. When SRP1, SRP0 = (1, 0), a power-down, power-up cycle will change SRP1, SRP0 to (0, 0) state.

2. This feature is available upon special order. Please contact Winbond for details.

7.1.8 Erase/Program Suspend Status (SUS)

The Suspend Status bit is a read only bit in the status register (S15) that is set to 1 after executing a

Erase/Program Suspend (75h) instruction. The SUS status bit is cleared to 0 by Erase/Program Resume

(7Ah) instruction as well as a power-down, power-up cycle.

7.1.9 Security Register Lock Bits (LB3, LB2, LB1, LB0)

The Security Register Lock Bits (LB3, LB2, LB1, LB0) are non-volatile One Time Program (OTP) bits in

Status Register (S13, S12, S11, S10) that provide the write protect control and status to the Security

Registers. The default state of LB3-0 is 0, Security Registers are unlocked. LB3-0 can be set to 1

individually using the Write Status Register instruction. LB3-0 are One Time Programmable (OTP), once

it’s set to 1, the corresponding 256-Byte Security Register will become read-only permanently.

7.1.10 Quad Enable (QE)

The Quad Enable (QE) bit is a non-volatile read/write bit in the status register (S9) that allows Quad SPI

and QPI operation. When the QE bit is set to a 0 state (factory default), the /WP pin and /HOLD are

enabled. When the QE bit is set to a 1, the Quad IO2 and IO3 pins are enabled, and /WP and /HOLD

functions are disabled.

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Publication Release Date: September 1, 2014

Revision J

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