25Q16 View Datasheet(PDF) - Winbond
Part Name
Description
Manufacturer
25Q16 Datasheet PDF : 61 Pages
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W25Q80, W25Q16, W25Q32
10.2.28 Mode Bit Reset (FFh or FFFFh)
For Fast Read Dual/Quad I/O operations, Mode Bits (M7-0) are implemented to further reduce
instruction overhead. By setting the Mode Bits (M7-0) to “Ax” hex, the next Fast Read Dual/Quad I/O
operation does not require the BBh/EBh instruction code (See 10.2.12 Fast Read Dual I/O and 10.2.13
Fast Read Quad I/O for detail descriptions).
If the system controller is Reset during operation it will likely send a standard SPI instruction, such
as Read ID (9Fh) or Fast Read (0Bh), to the 25Q16/32/80. However, as with most SPI Serial Flash
memories, the 25Q80/16/32 does not have a hardware Reset pin, so if Mode bits are set to “Ax”
hex, the 25Q80/16/32 will not recognize any standard SPI instructions. To address this possibility, it is
recommended to issue a Mode Bit Reset instruction as the first instruction after a system Reset. Doing
so will release the Mode Bits for the “Ax” hex state and allow Standard SPI instructions to be
recognized. The Mode Bits Reset instruction is shown in figure 29.
/CS
CLK
Mode 3
Mode 0
IO0
IO1
IO2
IO3
Mode Bit Reset
for Quad I/O
Mode Bit Reset
for Dual I/O
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
Mode 3
Mode 0
FFh
FFh
Don’t Care
Don’t Care
Don’t Care
Figure 29. Mode Bit Reset for Fast Read Dual/Quad I/O
To reset Mode Bit during Quad I/O operation, only eight clocks are needed. The instruction is “FFh”. To
reset Mode Bit during Dual I/O operation, sixteen clocks are needed to shift in instruction “FFFFh”.
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Publication Release Date: September 26, 2007
Preliminary - Revision B
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