W25P20-VSNI-G View Datasheet(PDF) - Winbond
Part Name
Description
Manufacturer
W25P20-VSNI-G Datasheet PDF : 35 Pages
| |||
W25P10, W25P20 AND W25P40
7.1.6 Status Register Memory Protection
STATUS REGISTER(1)
W25P40 (4M-BIT) MEMORY PROTECTION
BP2 BP1 BP0 SECTOR(S)
ADDRESSES
0
0
0
NONE
NONE
0
0
1
7
070000h - 07FFFFh
0
1
0
6 and 7
060000h - 07FFFFh
0
1
1
4 thru 7
040000h - 07FFFFh
1
x
x
ALL
000000h - 07FFFFh
DENSITY (KB)
NONE
512K-bit
1M-bit
2M-bit
4M-bit
PORTION
NONE
Upper 1/8
Upper 1/4
Upper 1/2
ALL
STATUS REGISTER(1)
BP2 BP1 BP0
x
0
0
x
0
1
x
1
0
x
1
1
SECTOR(S)
NONE
3
2 and 3
ALL
W25P20 (2M-BIT) MEMORY PROTECTION
ADDRESSES
NONE
030000h - 03FFFFh
020000h - 03FFFFh
000000h - 03FFFFh
DENSITY (KB)
NONE
512K-bit
1M-bit
2M-bit
PORTION
NONE
Upper 1/4
Upper 1/2
ALL
STATUS REGISTER(1)
BP2 BP1 BP0
x
0
x
x
1
0
x
1
1
SECTOR(S)
NONE
NONE
ALL
W25P10 (1M-BIT) MEMORY PROTECTION
ADDRESSES
NONE
NONE
000000h - 01FFFFh
DENSITY (KB)
NONE
NONE
1M-bit
Note:
1. x = don’t care
PORTION
NONE
NONE
ALL
7.2 INSTRUCTIONS
The instruction set of the W25P10/20/40 consists of twelve basic instructions that are fully controlled
through the SPI bus (see Instruction Set table). Instructions are initiated with the falling edge of Chip
Select (/CS). The first byte of data clocked into the DI input provides the instruction code. Data on the
DI input is sampled on the rising edge of clock with most significant bit (MSB) first.
Instructions vary in length from a single byte to several bytes and may be followed by address bytes,
data bytes, dummy bytes (don’t care), and in some cases, a combination. Instructions are completed
with the rising edge of edge /CS. Clock relative timing diagrams for each instruction are included in
figures 4 through 16. All read instructions can be completed after any clocked bit. However, all
instructions that Write, Program or Erase must complete on a byte boundary (/CS driven high after a
full 8-bits have been clocked) otherwise the instruction will be terminated. This feature further protects
the device from inadvertent writes. Additionally, while the memory is being programmed or erased, or
when the Status Register is being written, all instructions except for Read Status Register will be
ignored until the program or erase cycle has completed.
Publication Release Date: November 28, 2005
- 11 -
Revision M
|
|
Share Link: 