µPD161831
6.2.2 Serial interface between µPD161831 and back panel LCD Controller Driver
This 8-bit serial interface is used to control the back panel LCD.
When a function to transfer data to the back panel LCD is selected by a command (A6 bit = 1), the chip select
signals (/CS1 and CS2) for the back panel LCD are asserted. When data is input from the SCLK and SI pins to
transfer parameters and data, the polarity of the back panel LCD clock (SCLK_SUB) is the low level (high-level start)
and data is output from the back panel serial data output line (SO_SUB) at the falling edge of the clock, regardless of
the polarity and edge specification of the clock input to SCLK.
Bit A0 of the command can be used to specify the level to be output to the A0 pin. If “command specification” is
specified by the A0 bit (A0 bit = 0), the A0 pin outputs a low level when the data of the parameter & data register is
transferred. If “parameter setting” is specified by the A0 bit (A0 bit = 1), the A0 pin outputs a high level when the data
of the parameter & data register is transferred.
This interface can be used even in the standby mode.
The transfer operation is illustrated below.
Figure 6−5. Serial Interface Signal Chart (Access to Back Panel LCD, SCLEG0 = SCLEG1 = H)
<MCU to µPD161831>
LCDCS
SCLK
SDI
A7
A6 A5 A4 A3 A2 A1 A0
<µPD161831 to Sub LCD controller driver>
/CS1
CS2
SCLK_SUB
SO_SUB
A0
D7 D6 D5 D4 D3 D2 D1 D0
Command & data transfer
D7 D6 D5 D4 D3 D2 D1 D0
Serial interface operation specification register transfer
Transfer to back panel
46
Preliminary Product Information S16269EJ2V0PM