µPD161831
4. REGISTERS
The µPD161831 can set a horizontal period and vertical period by using registers. The serial interface is used to
specify a register and set values to it. Figure 4−1 shows a simplified timing chart of the serial interface.
LCDCS
SCLK
SI
Figure 4−1. Timing Chart of Serial Interface
A7 A6 A5 A4 A3 A2 A1 A0
D7 D6 D5 D4 D3 D2 D1 D0
Serial interface operation specification transfer
- Specification of register
- Specification of read or write
- Selection of back panel LCD function
- Selection of serial interface for gate
Command & data transfer
- Selection of command register
- Transfer of set values of command register
This serial interface has an 8-bit configuration. Note that it is accessed twice in 8-bit units to set a register.
The first 8-bit data (A7 to A0 in figure 4−1) is transferred to the “serial interface operation specification register”.
The serial interface operation specification register specifies the transfer operation of the next 8 bits (D7 to D0 in
figure 4−1). The second 8-bit data selects a command register or transfers the set value of the command register.
In addition, while writing a setup in command register with the 8-bit transfer + 8-bit (A7 to A0 + D7 to D0) which
selects command register or transferring of 8 bit + 8-bit transfer of readings (A7 to A0 + D7 to D0) (a total of 32 bits),
continue making chip select (LCDCS) active.
Table 4−1 indicates the function of the serial interface operation specification register. Table 4−2 shows the register
number and register name of each command register. Tables 4−3 and 4−5 to 4−24 describe the function of each
command register.
When the timing generator is used, there are three execution patterns for each command: Immediate execution
following setting, execution at the line following that where command was set, and execution at the frame following
that where command was set. In the case of execution at the next line and execution at the next frame, the concrete
command execution timing is as follows.
However, when the timing generator is not used, commands are executed at the first falling edge of DCK following
command transmission.
Execution from next line following command input (HSYNC, DOTCLK = low active)
<1> <2> <3> <4>
<1> <2> <3> <4>
DOTCLK
DOTCLK
HSYNC
Command input in above interval is executed at the next line.
↑
Command execution
Execution from next frame following command input (VSYNC, HSYNC, DOTCLK = low active)
<1> <2> <3> <4>
DOTCLK
DOTCLK
<1> <2> <3> <4>
HSYNC
VSYNC
Command input in above interval is executed at the next line.
Preliminary Product Information S16269EJ2V0PM
↑
Command execution
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